forked from luck/tmp_suning_uos_patched
73b4390fb2
Signed-off-by: Phil Sutter <n0-1@freewrt.org> Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
142 lines
4.5 KiB
C
142 lines
4.5 KiB
C
/*
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* Definitions for the DDR registers
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*
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* Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
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* Copyright 2008 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef _ASM_RC32434_DDR_H_
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#define _ASM_RC32434_DDR_H_
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#include <asm/mach-rc32434/rb.h>
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/* DDR register structure */
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struct ddr_ram {
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u32 ddrbase;
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u32 ddrmask;
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u32 res1;
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u32 res2;
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u32 ddrc;
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u32 ddrabase;
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u32 ddramask;
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u32 ddramap;
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u32 ddrcust;
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u32 ddrrdc;
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u32 ddrspare;
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};
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#define DDR0_PHYS_ADDR 0x18018000
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/* DDR banks masks */
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#define DDR_MASK 0xffff0000
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#define DDR0_BASE_MSK DDR_MASK
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#define DDR1_BASE_MSK DDR_MASK
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/* DDR bank0 registers */
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#define RC32434_DDR0_ATA_BIT 5
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#define RC32434_DDR0_ATA_MSK 0x000000E0
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#define RC32434_DDR0_DBW_BIT 8
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#define RC32434_DDR0_DBW_MSK 0x00000100
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#define RC32434_DDR0_WR_BIT 9
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#define RC32434_DDR0_WR_MSK 0x00000600
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#define RC32434_DDR0_PS_BIT 11
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#define RC32434_DDR0_PS_MSK 0x00001800
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#define RC32434_DDR0_DTYPE_BIT 13
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#define RC32434_DDR0_DTYPE_MSK 0x0000e000
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#define RC32434_DDR0_RFC_BIT 16
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#define RC32434_DDR0_RFC_MSK 0x000f0000
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#define RC32434_DDR0_RP_BIT 20
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#define RC32434_DDR0_RP_MSK 0x00300000
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#define RC32434_DDR0_AP_BIT 22
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#define RC32434_DDR0_AP_MSK 0x00400000
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#define RC32434_DDR0_RCD_BIT 23
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#define RC32434_DDR0_RCD_MSK 0x01800000
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#define RC32434_DDR0_CL_BIT 25
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#define RC32434_DDR0_CL_MSK 0x06000000
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#define RC32434_DDR0_DBM_BIT 27
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#define RC32434_DDR0_DBM_MSK 0x08000000
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#define RC32434_DDR0_SDS_BIT 28
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#define RC32434_DDR0_SDS_MSK 0x10000000
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#define RC32434_DDR0_ATP_BIT 29
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#define RC32434_DDR0_ATP_MSK 0x60000000
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#define RC32434_DDR0_RE_BIT 31
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#define RC32434_DDR0_RE_MSK 0x80000000
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/* DDR bank C registers */
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#define RC32434_DDRC_MSK(x) BIT_TO_MASK(x)
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#define RC32434_DDRC_CES_BIT 0
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#define RC32434_DDRC_ACE_BIT 1
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/* Custom DDR bank registers */
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#define RC32434_DCST_MSK(x) BIT_TO_MASK(x)
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#define RC32434_DCST_CS_BIT 0
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#define RC32434_DCST_CS_MSK 0x00000003
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#define RC32434_DCST_WE_BIT 2
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#define RC32434_DCST_RAS_BIT 3
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#define RC32434_DCST_CAS_BIT 4
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#define RC32434_DSCT_CKE_BIT 5
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#define RC32434_DSCT_BA_BIT 6
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#define RC32434_DSCT_BA_MSK 0x000000c0
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/* DDR QSC registers */
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#define RC32434_QSC_DM_BIT 0
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#define RC32434_QSC_DM_MSK 0x00000003
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#define RC32434_QSC_DQSBS_BIT 2
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#define RC32434_QSC_DQSBS_MSK 0x000000fc
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#define RC32434_QSC_DB_BIT 8
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#define RC32434_QSC_DB_MSK 0x00000100
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#define RC32434_QSC_DBSP_BIT 9
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#define RC32434_QSC_DBSP_MSK 0x01fffe00
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#define RC32434_QSC_BDP_BIT 25
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#define RC32434_QSC_BDP_MSK 0x7e000000
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/* DDR LLC registers */
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#define RC32434_LLC_EAO_BIT 0
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#define RC32434_LLC_EAO_MSK 0x00000001
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#define RC32434_LLC_EO_BIT 1
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#define RC32434_LLC_EO_MSK 0x0000003e
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#define RC32434_LLC_FS_BIT 6
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#define RC32434_LLC_FS_MSK 0x000000c0
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#define RC32434_LLC_AS_BIT 8
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#define RC32434_LLC_AS_MSK 0x00000700
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#define RC32434_LLC_SP_BIT 11
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#define RC32434_LLC_SP_MSK 0x001ff800
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/* DDR LLFC registers */
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#define RC32434_LLFC_MSK(x) BIT_TO_MASK(x)
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#define RC32434_LLFC_MEN_BIT 0
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#define RC32434_LLFC_EAN_BIT 1
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#define RC32434_LLFC_FF_BIT 2
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/* DDR DLLTA registers */
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#define RC32434_DLLTA_ADDR_BIT 2
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#define RC32434_DLLTA_ADDR_MSK 0xfffffffc
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/* DDR DLLED registers */
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#define RC32434_DLLED_MSK(x) BIT_TO_MASK(x)
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#define RC32434_DLLED_DBE_BIT 0
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#define RC32434_DLLED_DTE_BIT 1
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#endif /* _ASM_RC32434_DDR_H_ */
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