Stafford Horne 489e0f802d openrisc: add 1 and 2 byte cmpxchg support ... OpenRISC only supports hardware instructions that perform 4 byte atomic operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte implementations are needed. To do this we leverage the 4 byte atomic operations and shift/mask the 1 and 2 byte areas as needed. This heavily borrows ideas and routines from sh and mips, which do something similar. Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Stafford Horne <shorne@gmail.com>		2017-11-03 14:01:12 +09:00
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boot/dts	openrisc: dts: or1ksim: Add stdout-path	2017-10-30 21:37:51 +09:00
configs	openrisc: defconfig: Cleanup from old Kconfig options	2017-07-08 04:35:30 +09:00
include	openrisc: add 1 and 2 byte cmpxchg support	2017-11-03 14:01:12 +09:00
kernel	openrisc: use shadow registers to save regs on exception	2017-11-03 14:01:11 +09:00
lib	openrisc: Switch to use export.h instead of module.h	2017-05-15 22:02:33 +09:00
mm	sched/headers: Prepare for new header dependencies before moving code to <linux/sched/signal.h>	2017-03-02 08:42:29 +01:00
Kconfig	openrisc: use shadow registers to save regs on exception	2017-11-03 14:01:11 +09:00
Makefile