forked from luck/tmp_suning_uos_patched
ed21cfe207
On XLR/XLS, the cpu cores communicate with fast on-chip devices (e.g. network accelerator, security engine etc.) using the Fast Messaging Network(FMN). The FMN queues and credits needs to be configured and intialized before it can be used. The co-processor 2 on XLR/XLS CPU cores has registers for FMN access, and the XLR/XLS has custom instructions for sending and loading messages. The FMN can deliver also per-cpu interrupts when messages are available at the CPU. This patch adds FMN initialization, adds interrupt setup and handling, and also provides support for sending and receiving FMN messages. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4468 Signed-off-by: John Crispin <blogic@openwrt.org>
164 lines
4.3 KiB
C
164 lines
4.3 KiB
C
/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/serial_8250.h>
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#include <linux/pm.h>
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#include <linux/bootmem.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/bootinfo.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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uint64_t nlm_io_base;
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struct nlm_soc_info nlm_nodes[NLM_NR_NODES];
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cpumask_t nlm_cpumask = CPU_MASK_CPU0;
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unsigned int nlm_threads_per_core;
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extern u32 __dtb_start[];
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static void nlm_linux_exit(void)
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{
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uint64_t sysbase = nlm_get_node(0)->sysbase;
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nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
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for ( ; ; )
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cpu_wait();
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}
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void __init plat_mem_setup(void)
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{
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void *fdtp;
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panic_timeout = 5;
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_machine_restart = (void (*)(char *))nlm_linux_exit;
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_machine_halt = nlm_linux_exit;
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pm_power_off = nlm_linux_exit;
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/*
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* If no FDT pointer is passed in, use the built-in FDT.
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* device_tree_init() does not handle CKSEG0 pointers in
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* 64-bit, so convert pointer.
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*/
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fdtp = (void *)(long)fw_arg0;
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if (!fdtp)
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fdtp = __dtb_start;
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fdtp = phys_to_virt(__pa(fdtp));
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early_init_devtree(fdtp);
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}
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const char *get_system_type(void)
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{
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return "Netlogic XLP Series";
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}
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void __init prom_free_prom_memory(void)
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{
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/* Nothing yet */
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}
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void xlp_mmu_init(void)
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{
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/* enable extended TLB and Large Fixed TLB */
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write_c0_config6(read_c0_config6() | 0x24);
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/* set page mask of Fixed TLB in config7 */
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write_c0_config7(PM_DEFAULT_MASK >>
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(13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
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}
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void nlm_percpu_init(int hwcpuid)
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{
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}
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void __init prom_init(void)
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{
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nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
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xlp_mmu_init();
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nlm_node_init(0);
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#ifdef CONFIG_SMP
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cpumask_setall(&nlm_cpumask);
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nlm_wakeup_secondary_cpus();
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/* update TLB size after waking up threads */
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current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
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register_smp_ops(&nlm_smp_ops);
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#endif
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}
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void __init device_tree_init(void)
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{
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unsigned long base, size;
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if (!initial_boot_params)
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return;
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base = virt_to_phys((void *)initial_boot_params);
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size = be32_to_cpu(initial_boot_params->totalsize);
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/* Before we do anything, lets reserve the dt blob */
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reserve_bootmem(base, size, BOOTMEM_DEFAULT);
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unflatten_device_tree();
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/* free the space reserved for the dt blob */
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free_bootmem(base, size);
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}
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static struct of_device_id __initdata xlp_ids[] = {
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{ .compatible = "simple-bus", },
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{},
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};
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int __init xlp8xx_ds_publish_devices(void)
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{
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if (!of_have_populated_dt())
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return 0;
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return of_platform_bus_probe(NULL, xlp_ids, NULL);
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}
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device_initcall(xlp8xx_ds_publish_devices);
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