forked from luck/tmp_suning_uos_patched
5175cb5894
This adds clock support to Loongson1B SoC using the common clock infrastructure. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
112 lines
2.8 KiB
C
112 lines
2.8 KiB
C
/*
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* Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <loongson1.h>
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#define OSC 33
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static DEFINE_SPINLOCK(_lock);
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static int ls1x_pll_clk_enable(struct clk_hw *hw)
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{
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return 0;
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}
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static void ls1x_pll_clk_disable(struct clk_hw *hw)
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{
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}
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static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 pll, rate;
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pll = __raw_readl(LS1X_CLK_PLL_FREQ);
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rate = ((12 + (pll & 0x3f)) * 1000000) +
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((((pll >> 8) & 0x3ff) * 1000000) >> 10);
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rate *= OSC;
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rate >>= 1;
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return rate;
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}
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static const struct clk_ops ls1x_pll_clk_ops = {
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.enable = ls1x_pll_clk_enable,
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.disable = ls1x_pll_clk_disable,
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.recalc_rate = ls1x_pll_recalc_rate,
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};
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static struct clk * __init clk_register_pll(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags)
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{
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struct clk_hw *hw;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the divider */
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hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
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if (!hw) {
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pr_err("%s: could not allocate clk_hw\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &ls1x_pll_clk_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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hw->init = &init;
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/* register the clock */
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clk = clk_register(dev, hw);
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if (IS_ERR(clk))
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kfree(hw);
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return clk;
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}
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void __init ls1x_clk_init(void)
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{
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struct clk *clk;
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clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
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clk_prepare_enable(clk);
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clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
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CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
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DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
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clk_prepare_enable(clk);
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clk_register_clkdev(clk, "cpu", NULL);
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clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
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CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
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DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
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clk_prepare_enable(clk);
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clk_register_clkdev(clk, "dc", NULL);
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clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
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CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
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DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
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clk_prepare_enable(clk);
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clk_register_clkdev(clk, "ahb", NULL);
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clk_register_clkdev(clk, "stmmaceth", NULL);
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clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2);
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clk_prepare_enable(clk);
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clk_register_clkdev(clk, "apb", NULL);
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clk_register_clkdev(clk, "serial8250", NULL);
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}
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