kernel_optimize_test/drivers/soc
Yash Shah 4a3a373312
riscv: Add support to determine no. of L2 cache way enabled
In order to determine the number of L2 cache ways enabled at runtime,
implement a private attribute ("number_of_ways_enabled"). Reading this
attribute returns the number of enabled L2 cache ways at runtime.

Using riscv_set_cacheinfo_ops() hook a custom function, that returns
this private attribute, to the generic ops structure which is used by
cache_get_priv_group() in cacheinfo framework.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-20 15:05:10 -07:00
..
actions
amlogic
aspeed
atmel
bcm
dove
fsl soc: fsl: dpio: avoid stack usage warning 2020-04-17 17:20:44 +02:00
gemini
imx soc: imx8: select SOC_BUS 2020-04-17 17:20:44 +02:00
ixp4xx
kendryte riscv: K210: Add a built-in device tree 2020-05-18 11:38:06 -07:00
lantiq
mediatek
qcom
renesas ARM: driver updates 2020-04-03 15:05:35 -07:00
rockchip
samsung
sifive riscv: Add support to determine no. of L2 cache way enabled 2020-05-20 15:05:10 -07:00
sunxi
tegra
ti
ux500
versatile
xilinx drivers: soc: xilinx: fix firmware driver Kconfig dependency 2020-04-15 08:15:55 +02:00
zte
Kconfig
Makefile RISC-V Patches for the 5.7 Merge Window, Part 1 2020-04-09 10:51:30 -07:00