forked from luck/tmp_suning_uos_patched
f25234f1c2
`port' is used as index for writing to pins during allocation/deallocation. It should be positive. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
387 lines
9.7 KiB
C
387 lines
9.7 KiB
C
/*
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* Allocator for I/O pins. All pins are allocated to GPIO at bootup.
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* Unassigned pins and GPIO pins can be allocated to a fixed interface
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* or the I/O processor instead.
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*
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* Copyright (c) 2005-2007 Axis Communications AB.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/spinlock.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <pinmux.h>
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#include <hwregs/pinmux_defs.h>
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#include <hwregs/clkgen_defs.h>
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#undef DEBUG
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#define PINS 80
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#define PORT_PINS 32
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#define PORTS 3
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static char pins[PINS];
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static DEFINE_SPINLOCK(pinmux_lock);
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static void crisv32_pinmux_set(int port);
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int
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crisv32_pinmux_init(void)
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{
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static int initialized;
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if (!initialized) {
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initialized = 1;
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REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0);
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crisv32_pinmux_alloc(PORT_A, 0, 31, pinmux_gpio);
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crisv32_pinmux_alloc(PORT_B, 0, 31, pinmux_gpio);
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crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_gpio);
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}
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return 0;
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}
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int
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crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
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{
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int i;
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unsigned long flags;
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crisv32_pinmux_init();
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if (port >= PORTS)
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return -EINVAL;
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spin_lock_irqsave(&pinmux_lock, flags);
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for (i = first_pin; i <= last_pin; i++) {
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if ((pins[port * PORT_PINS + i] != pinmux_none) &&
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(pins[port * PORT_PINS + i] != pinmux_gpio) &&
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(pins[port * PORT_PINS + i] != mode)) {
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spin_unlock_irqrestore(&pinmux_lock, flags);
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#ifdef DEBUG
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panic("Pinmux alloc failed!\n");
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#endif
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return -EPERM;
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}
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}
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for (i = first_pin; i <= last_pin; i++)
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pins[port * PORT_PINS + i] = mode;
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crisv32_pinmux_set(port);
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return 0;
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}
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int
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crisv32_pinmux_alloc_fixed(enum fixed_function function)
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{
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int ret = -EINVAL;
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char saved[sizeof pins];
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unsigned long flags;
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spin_lock_irqsave(&pinmux_lock, flags);
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/* Save internal data for recovery */
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memcpy(saved, pins, sizeof pins);
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crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
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reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
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reg_clkgen_rw_clk_ctrl clk_ctrl = REG_RD(clkgen, regi_clkgen,
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rw_clk_ctrl);
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switch (function) {
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case pinmux_eth:
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clk_ctrl.eth = regk_clkgen_yes;
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clk_ctrl.dma0_1_eth = regk_clkgen_yes;
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ret = crisv32_pinmux_alloc(PORT_B, 8, 23, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_B, 24, 25, pinmux_fixed);
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hwprot.eth = hwprot.eth_mdio = regk_pinmux_yes;
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break;
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case pinmux_geth:
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ret = crisv32_pinmux_alloc(PORT_B, 0, 7, pinmux_fixed);
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hwprot.geth = regk_pinmux_yes;
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break;
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case pinmux_tg_cmos:
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clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
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ret = crisv32_pinmux_alloc(PORT_B, 27, 29, pinmux_fixed);
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hwprot.tg_clk = regk_pinmux_yes;
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break;
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case pinmux_tg_ccd:
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clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
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ret = crisv32_pinmux_alloc(PORT_B, 27, 31, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_fixed);
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hwprot.tg = hwprot.tg_clk = regk_pinmux_yes;
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break;
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case pinmux_vout:
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clk_ctrl.strdma0_2_video = regk_clkgen_yes;
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ret = crisv32_pinmux_alloc(PORT_A, 8, 18, pinmux_fixed);
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hwprot.vout = hwprot.vout_sync = regk_pinmux_yes;
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break;
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case pinmux_ser1:
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clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
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ret = crisv32_pinmux_alloc(PORT_A, 24, 25, pinmux_fixed);
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hwprot.ser1 = regk_pinmux_yes;
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break;
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case pinmux_ser2:
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clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
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ret = crisv32_pinmux_alloc(PORT_A, 26, 27, pinmux_fixed);
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hwprot.ser2 = regk_pinmux_yes;
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break;
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case pinmux_ser3:
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clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
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ret = crisv32_pinmux_alloc(PORT_A, 28, 29, pinmux_fixed);
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hwprot.ser3 = regk_pinmux_yes;
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break;
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case pinmux_ser4:
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clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
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ret = crisv32_pinmux_alloc(PORT_A, 30, 31, pinmux_fixed);
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hwprot.ser4 = regk_pinmux_yes;
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break;
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case pinmux_sser:
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clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
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ret = crisv32_pinmux_alloc(PORT_A, 19, 23, pinmux_fixed);
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hwprot.sser = regk_pinmux_yes;
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break;
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case pinmux_pio:
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hwprot.pio = regk_pinmux_yes;
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ret = 0;
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break;
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case pinmux_pwm0:
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ret = crisv32_pinmux_alloc(PORT_A, 30, 30, pinmux_fixed);
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hwprot.pwm0 = regk_pinmux_yes;
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break;
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case pinmux_pwm1:
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ret = crisv32_pinmux_alloc(PORT_A, 31, 31, pinmux_fixed);
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hwprot.pwm1 = regk_pinmux_yes;
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break;
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case pinmux_pwm2:
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ret = crisv32_pinmux_alloc(PORT_B, 26, 26, pinmux_fixed);
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hwprot.pwm2 = regk_pinmux_yes;
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break;
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case pinmux_i2c0:
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ret = crisv32_pinmux_alloc(PORT_A, 0, 1, pinmux_fixed);
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hwprot.i2c0 = regk_pinmux_yes;
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break;
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case pinmux_i2c1:
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ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
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hwprot.i2c1 = regk_pinmux_yes;
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break;
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case pinmux_i2c1_3wire:
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ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_A, 7, 7, pinmux_fixed);
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hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_yes;
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break;
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case pinmux_i2c1_sda1:
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ret = crisv32_pinmux_alloc(PORT_A, 2, 4, pinmux_fixed);
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hwprot.i2c1 = hwprot.i2c1_sda1 = regk_pinmux_yes;
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break;
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case pinmux_i2c1_sda2:
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ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_A, 5, 5, pinmux_fixed);
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hwprot.i2c1 = hwprot.i2c1_sda2 = regk_pinmux_yes;
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break;
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case pinmux_i2c1_sda3:
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ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_A, 6, 6, pinmux_fixed);
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hwprot.i2c1 = hwprot.i2c1_sda3 = regk_pinmux_yes;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (!ret) {
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REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
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REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
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} else
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memcpy(pins, saved, sizeof pins);
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return ret;
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}
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void
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crisv32_pinmux_set(int port)
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{
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int i;
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int gpio_val = 0;
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int iop_val = 0;
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int pin = port * PORT_PINS;
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for (i = 0; (i < PORT_PINS) && (pin < PINS); i++, pin++) {
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if (pins[pin] == pinmux_gpio)
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gpio_val |= (1 << i);
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else if (pins[pin] == pinmux_iop)
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iop_val |= (1 << i);
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}
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REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port,
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gpio_val);
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REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port,
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iop_val);
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#ifdef DEBUG
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crisv32_pinmux_dump();
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#endif
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}
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int
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crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
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{
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int i;
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unsigned long flags;
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crisv32_pinmux_init();
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if (port > PORTS || port < 0)
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return -EINVAL;
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spin_lock_irqsave(&pinmux_lock, flags);
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for (i = first_pin; i <= last_pin; i++)
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pins[port * PORT_PINS + i] = pinmux_none;
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crisv32_pinmux_set(port);
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return 0;
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}
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int
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crisv32_pinmux_dealloc_fixed(enum fixed_function function)
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{
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int ret = -EINVAL;
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char saved[sizeof pins];
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unsigned long flags;
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spin_lock_irqsave(&pinmux_lock, flags);
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/* Save internal data for recovery */
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memcpy(saved, pins, sizeof pins);
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crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
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reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
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switch (function) {
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case pinmux_eth:
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ret = crisv32_pinmux_dealloc(PORT_B, 8, 23);
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ret |= crisv32_pinmux_dealloc(PORT_B, 24, 25);
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ret |= crisv32_pinmux_dealloc(PORT_B, 0, 7);
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hwprot.eth = hwprot.eth_mdio = hwprot.geth = regk_pinmux_no;
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break;
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case pinmux_tg_cmos:
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ret = crisv32_pinmux_dealloc(PORT_B, 27, 29);
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hwprot.tg_clk = regk_pinmux_no;
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break;
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case pinmux_tg_ccd:
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ret = crisv32_pinmux_dealloc(PORT_B, 27, 31);
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ret |= crisv32_pinmux_dealloc(PORT_C, 0, 15);
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hwprot.tg = hwprot.tg_clk = regk_pinmux_no;
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break;
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case pinmux_vout:
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ret = crisv32_pinmux_dealloc(PORT_A, 8, 18);
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hwprot.vout = hwprot.vout_sync = regk_pinmux_no;
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break;
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case pinmux_ser1:
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ret = crisv32_pinmux_dealloc(PORT_A, 24, 25);
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hwprot.ser1 = regk_pinmux_no;
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break;
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case pinmux_ser2:
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ret = crisv32_pinmux_dealloc(PORT_A, 26, 27);
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hwprot.ser2 = regk_pinmux_no;
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break;
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case pinmux_ser3:
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ret = crisv32_pinmux_dealloc(PORT_A, 28, 29);
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hwprot.ser3 = regk_pinmux_no;
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break;
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case pinmux_ser4:
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ret = crisv32_pinmux_dealloc(PORT_A, 30, 31);
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hwprot.ser4 = regk_pinmux_no;
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break;
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case pinmux_sser:
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ret = crisv32_pinmux_dealloc(PORT_A, 19, 23);
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hwprot.sser = regk_pinmux_no;
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break;
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case pinmux_pwm0:
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ret = crisv32_pinmux_dealloc(PORT_A, 30, 30);
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hwprot.pwm0 = regk_pinmux_no;
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break;
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case pinmux_pwm1:
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ret = crisv32_pinmux_dealloc(PORT_A, 31, 31);
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hwprot.pwm1 = regk_pinmux_no;
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break;
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case pinmux_pwm2:
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ret = crisv32_pinmux_dealloc(PORT_B, 26, 26);
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hwprot.pwm2 = regk_pinmux_no;
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break;
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case pinmux_i2c0:
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ret = crisv32_pinmux_dealloc(PORT_A, 0, 1);
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hwprot.i2c0 = regk_pinmux_no;
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break;
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case pinmux_i2c1:
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ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
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hwprot.i2c1 = regk_pinmux_no;
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break;
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case pinmux_i2c1_3wire:
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ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
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ret |= crisv32_pinmux_dealloc(PORT_A, 7, 7);
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hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_no;
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break;
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case pinmux_i2c1_sda1:
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ret = crisv32_pinmux_dealloc(PORT_A, 2, 4);
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hwprot.i2c1_sda1 = regk_pinmux_no;
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break;
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case pinmux_i2c1_sda2:
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ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
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ret |= crisv32_pinmux_dealloc(PORT_A, 5, 5);
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hwprot.i2c1_sda2 = regk_pinmux_no;
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break;
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case pinmux_i2c1_sda3:
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ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
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ret |= crisv32_pinmux_dealloc(PORT_A, 6, 6);
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hwprot.i2c1_sda3 = regk_pinmux_no;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (!ret)
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REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
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else
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memcpy(pins, saved, sizeof pins);
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return ret;
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}
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void
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crisv32_pinmux_dump(void)
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{
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int i, j;
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int pin = 0;
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crisv32_pinmux_init();
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for (i = 0; i < PORTS; i++) {
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pin++;
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printk(KERN_DEBUG "Port %c\n", 'A'+i);
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for (j = 0; (j < PORT_PINS) && (pin < PINS); j++, pin++)
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printk(KERN_DEBUG
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" Pin %d = %d\n", j, pins[i * PORT_PINS + j]);
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}
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}
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__initcall(crisv32_pinmux_init);
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