forked from luck/tmp_suning_uos_patched
4b3e975e4a
The idle loop goes to sleep using the WAIT instruction if !need_resched().
This has is suffering from from a race condition that if if just after
need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but
we've just completed the test so go to sleep anyway. This would be
trivial to fix by just disabling interrupts during that sequence as in:
local_irq_disable();
if (!need_resched())
__asm__("wait");
local_irq_enable();
but the processor architecture leaves it undefined if a processor calling
WAIT with interrupts disabled will ever restart its pipeline and indeed
some processors have made use of the freedom provided by the architecture
definition. This has been resolved and the Config7.WII bit indicates that
the use of WAIT is safe on 24K, 24KE and 34K cores. It also is safe on
74K starting revision 2.1.0 so enable the use of WAIT with interrupts
disabled for 74K based on a c0_prid of at least that.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
787 lines
18 KiB
C
787 lines
18 KiB
C
/*
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* Processor capabilities determination functions.
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*
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* Copyright (C) xxxx the Anonymous
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* Copyright (C) 1994 - 2006 Ralf Baechle
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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* Copyright (C) 2001, 2004 MIPS Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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#include <linux/stddef.h>
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#include <asm/bugs.h>
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#include <asm/cpu.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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/*
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* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
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* the implementation of the "wait" feature differs between CPU families. This
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* points to the function that implements CPU specific wait.
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* The wait instruction stops the pipeline and reduces the power consumption of
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* the CPU very much.
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*/
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void (*cpu_wait)(void) = NULL;
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static void r3081_wait(void)
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{
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unsigned long cfg = read_c0_conf();
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write_c0_conf(cfg | R30XX_CONF_HALT);
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}
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static void r39xx_wait(void)
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{
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local_irq_disable();
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if (!need_resched())
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write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
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local_irq_enable();
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}
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/*
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* There is a race when WAIT instruction executed with interrupt
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* enabled.
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* But it is implementation-dependent wheter the pipelie restarts when
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* a non-enabled interrupt is requested.
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*/
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static void r4k_wait(void)
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{
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__asm__(" .set mips3 \n"
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" wait \n"
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" .set mips0 \n");
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}
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/*
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* This variant is preferable as it allows testing need_resched and going to
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* sleep depending on the outcome atomically. Unfortunately the "It is
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* implementation-dependent whether the pipeline restarts when a non-enabled
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* interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
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* using this version a gamble.
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*/
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static void r4k_wait_irqoff(void)
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{
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local_irq_disable();
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if (!need_resched())
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__asm__(" .set mips3 \n"
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" wait \n"
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" .set mips0 \n");
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local_irq_enable();
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}
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/* The Au1xxx wait is available only if using 32khz counter or
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* external timer source, but specifically not CP0 Counter. */
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int allow_au1k_wait;
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static void au1k_wait(void)
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{
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/* using the wait instruction makes CP0 counter unusable */
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__asm__(" .set mips3 \n"
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" cache 0x14, 0(%0) \n"
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" cache 0x14, 32(%0) \n"
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" sync \n"
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" nop \n"
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" wait \n"
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" nop \n"
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" nop \n"
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" nop \n"
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" nop \n"
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" .set mips0 \n"
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: : "r" (au1k_wait));
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}
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static int __initdata nowait = 0;
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static int __init wait_disable(char *s)
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{
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nowait = 1;
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return 1;
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}
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__setup("nowait", wait_disable);
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static inline void check_wait(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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if (nowait) {
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printk("Wait instruction disabled.\n");
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return;
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}
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switch (c->cputype) {
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case CPU_R3081:
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case CPU_R3081E:
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cpu_wait = r3081_wait;
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break;
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case CPU_TX3927:
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cpu_wait = r39xx_wait;
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break;
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case CPU_R4200:
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/* case CPU_R4300: */
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case CPU_R4600:
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case CPU_R4640:
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case CPU_R4650:
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case CPU_R4700:
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case CPU_R5000:
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case CPU_NEVADA:
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case CPU_RM7000:
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case CPU_4KC:
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case CPU_4KEC:
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case CPU_4KSC:
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case CPU_5KC:
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case CPU_25KF:
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case CPU_PR4450:
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cpu_wait = r4k_wait;
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break;
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case CPU_24K:
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case CPU_34K:
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cpu_wait = r4k_wait;
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if (read_c0_config7() & MIPS_CONF7_WII)
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cpu_wait = r4k_wait_irqoff;
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break;
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case CPU_74K:
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cpu_wait = r4k_wait;
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if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
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cpu_wait = r4k_wait_irqoff;
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break;
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case CPU_TX49XX:
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cpu_wait = r4k_wait_irqoff;
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break;
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case CPU_AU1000:
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case CPU_AU1100:
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case CPU_AU1500:
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case CPU_AU1550:
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case CPU_AU1200:
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if (allow_au1k_wait)
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cpu_wait = au1k_wait;
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break;
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case CPU_20KC:
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/*
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* WAIT on Rev1.0 has E1, E2, E3 and E16.
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* WAIT on Rev2.0 and Rev3.0 has E16.
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* Rev3.1 WAIT is nop, why bother
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*/
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if ((c->processor_id & 0xff) <= 0x64)
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break;
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cpu_wait = r4k_wait;
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break;
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case CPU_RM9000:
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if ((c->processor_id & 0x00ff) >= 0x40)
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cpu_wait = r4k_wait;
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break;
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default:
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break;
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}
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}
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void __init check_bugs32(void)
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{
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check_wait();
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}
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/*
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* Probe whether cpu has config register by trying to play with
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* alternate cache bit and see whether it matters.
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* It's used by cpu_probe to distinguish between R3000A and R3081.
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*/
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static inline int cpu_has_confreg(void)
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{
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#ifdef CONFIG_CPU_R3000
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extern unsigned long r3k_cache_size(unsigned long);
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unsigned long size1, size2;
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unsigned long cfg = read_c0_conf();
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size1 = r3k_cache_size(ST0_ISC);
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write_c0_conf(cfg ^ R30XX_CONF_AC);
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size2 = r3k_cache_size(ST0_ISC);
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write_c0_conf(cfg);
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return size1 != size2;
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#else
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return 0;
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#endif
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}
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/*
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* Get the FPU Implementation/Revision.
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*/
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static inline unsigned long cpu_get_fpu_id(void)
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{
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unsigned long tmp, fpu_id;
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tmp = read_c0_status();
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__enable_fpu();
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fpu_id = read_32bit_cp1_register(CP1_REVISION);
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write_c0_status(tmp);
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return fpu_id;
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}
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/*
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* Check the CPU has an FPU the official way.
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*/
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static inline int __cpu_has_fpu(void)
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{
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return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
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}
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#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
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| MIPS_CPU_COUNTER)
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static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
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{
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_R2000:
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c->cputype = CPU_R2000;
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c->isa_level = MIPS_CPU_ISA_I;
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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MIPS_CPU_NOFPUEX;
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if (__cpu_has_fpu())
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c->options |= MIPS_CPU_FPU;
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c->tlbsize = 64;
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break;
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case PRID_IMP_R3000:
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if ((c->processor_id & 0xff) == PRID_REV_R3000A)
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if (cpu_has_confreg())
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c->cputype = CPU_R3081E;
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else
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c->cputype = CPU_R3000A;
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else
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c->cputype = CPU_R3000;
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c->isa_level = MIPS_CPU_ISA_I;
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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MIPS_CPU_NOFPUEX;
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if (__cpu_has_fpu())
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c->options |= MIPS_CPU_FPU;
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c->tlbsize = 64;
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break;
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case PRID_IMP_R4000:
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if (read_c0_config() & CONF_SC) {
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if ((c->processor_id & 0xff) >= PRID_REV_R4400)
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c->cputype = CPU_R4400PC;
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else
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c->cputype = CPU_R4000PC;
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} else {
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if ((c->processor_id & 0xff) >= PRID_REV_R4400)
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c->cputype = CPU_R4400SC;
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else
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c->cputype = CPU_R4000SC;
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}
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_WATCH | MIPS_CPU_VCE |
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MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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case PRID_IMP_VR41XX:
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switch (c->processor_id & 0xf0) {
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case PRID_REV_VR4111:
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c->cputype = CPU_VR4111;
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break;
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case PRID_REV_VR4121:
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c->cputype = CPU_VR4121;
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break;
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case PRID_REV_VR4122:
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if ((c->processor_id & 0xf) < 0x3)
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c->cputype = CPU_VR4122;
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else
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c->cputype = CPU_VR4181A;
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break;
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case PRID_REV_VR4130:
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if ((c->processor_id & 0xf) < 0x4)
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c->cputype = CPU_VR4131;
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else
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c->cputype = CPU_VR4133;
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break;
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default:
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printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
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c->cputype = CPU_VR41XX;
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break;
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}
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS;
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c->tlbsize = 32;
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break;
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case PRID_IMP_R4300:
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c->cputype = CPU_R4300;
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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c->tlbsize = 32;
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break;
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case PRID_IMP_R4600:
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c->cputype = CPU_R4600;
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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#if 0
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case PRID_IMP_R4650:
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/*
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* This processor doesn't have an MMU, so it's not
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* "real easy" to run Linux on it. It is left purely
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* for documentation. Commented out because it shares
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* it's c0_prid id number with the TX3900.
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*/
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c->cputype = CPU_R4650;
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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#endif
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case PRID_IMP_TX39:
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c->isa_level = MIPS_CPU_ISA_I;
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c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
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if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
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c->cputype = CPU_TX3927;
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c->tlbsize = 64;
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} else {
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switch (c->processor_id & 0xff) {
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case PRID_REV_TX3912:
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c->cputype = CPU_TX3912;
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c->tlbsize = 32;
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break;
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case PRID_REV_TX3922:
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c->cputype = CPU_TX3922;
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c->tlbsize = 64;
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break;
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default:
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c->cputype = CPU_UNKNOWN;
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break;
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}
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}
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break;
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case PRID_IMP_R4700:
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c->cputype = CPU_R4700;
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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case PRID_IMP_TX49:
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c->cputype = CPU_TX49XX;
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_LLSC;
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if (!(c->processor_id & 0x08))
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c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
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c->tlbsize = 48;
|
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break;
|
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case PRID_IMP_R5000:
|
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c->cputype = CPU_R5000;
|
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c->isa_level = MIPS_CPU_ISA_IV;
|
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
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MIPS_CPU_LLSC;
|
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c->tlbsize = 48;
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break;
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case PRID_IMP_R5432:
|
|
c->cputype = CPU_R5432;
|
|
c->isa_level = MIPS_CPU_ISA_IV;
|
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_WATCH | MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_R5500:
|
|
c->cputype = CPU_R5500;
|
|
c->isa_level = MIPS_CPU_ISA_IV;
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_WATCH | MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_NEVADA:
|
|
c->cputype = CPU_NEVADA;
|
|
c->isa_level = MIPS_CPU_ISA_IV;
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
|
|
c->tlbsize = 48;
|
|
break;
|
|
case PRID_IMP_R6000:
|
|
c->cputype = CPU_R6000;
|
|
c->isa_level = MIPS_CPU_ISA_II;
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 32;
|
|
break;
|
|
case PRID_IMP_R6000A:
|
|
c->cputype = CPU_R6000A;
|
|
c->isa_level = MIPS_CPU_ISA_II;
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 32;
|
|
break;
|
|
case PRID_IMP_RM7000:
|
|
c->cputype = CPU_RM7000;
|
|
c->isa_level = MIPS_CPU_ISA_IV;
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_LLSC;
|
|
/*
|
|
* Undocumented RM7000: Bit 29 in the info register of
|
|
* the RM7000 v2.0 indicates if the TLB has 48 or 64
|
|
* entries.
|
|
*
|
|
* 29 1 => 64 entry JTLB
|
|
* 0 => 48 entry JTLB
|
|
*/
|
|
c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
|
|
break;
|
|
case PRID_IMP_RM9000:
|
|
c->cputype = CPU_RM9000;
|
|
c->isa_level = MIPS_CPU_ISA_IV;
|
|
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_LLSC;
|
|
/*
|
|
* Bit 29 in the info register of the RM9000
|
|
* indicates if the TLB has 48 or 64 entries.
|
|
*
|
|
* 29 1 => 64 entry JTLB
|
|
* 0 => 48 entry JTLB
|
|
*/
|
|
c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
|
|
break;
|
|
case PRID_IMP_R8000:
|
|
c->cputype = CPU_R8000;
|
|
c->isa_level = MIPS_CPU_ISA_IV;
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
|
|
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
|
|
break;
|
|
case PRID_IMP_R10000:
|
|
c->cputype = CPU_R10000;
|
|
c->isa_level = MIPS_CPU_ISA_IV;
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
|
|
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 64;
|
|
break;
|
|
case PRID_IMP_R12000:
|
|
c->cputype = CPU_R12000;
|
|
c->isa_level = MIPS_CPU_ISA_IV;
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
|
|
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 64;
|
|
break;
|
|
case PRID_IMP_R14000:
|
|
c->cputype = CPU_R14000;
|
|
c->isa_level = MIPS_CPU_ISA_IV;
|
|
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
|
|
MIPS_CPU_FPU | MIPS_CPU_32FPR |
|
|
MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
|
|
MIPS_CPU_LLSC;
|
|
c->tlbsize = 64;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static char unknown_isa[] __initdata = KERN_ERR \
|
|
"Unsupported ISA type, c0.config0: %d.";
|
|
|
|
static inline unsigned int decode_config0(struct cpuinfo_mips *c)
|
|
{
|
|
unsigned int config0;
|
|
int isa;
|
|
|
|
config0 = read_c0_config();
|
|
|
|
if (((config0 & MIPS_CONF_MT) >> 7) == 1)
|
|
c->options |= MIPS_CPU_TLB;
|
|
isa = (config0 & MIPS_CONF_AT) >> 13;
|
|
switch (isa) {
|
|
case 0:
|
|
switch ((config0 & MIPS_CONF_AR) >> 10) {
|
|
case 0:
|
|
c->isa_level = MIPS_CPU_ISA_M32R1;
|
|
break;
|
|
case 1:
|
|
c->isa_level = MIPS_CPU_ISA_M32R2;
|
|
break;
|
|
default:
|
|
goto unknown;
|
|
}
|
|
break;
|
|
case 2:
|
|
switch ((config0 & MIPS_CONF_AR) >> 10) {
|
|
case 0:
|
|
c->isa_level = MIPS_CPU_ISA_M64R1;
|
|
break;
|
|
case 1:
|
|
c->isa_level = MIPS_CPU_ISA_M64R2;
|
|
break;
|
|
default:
|
|
goto unknown;
|
|
}
|
|
break;
|
|
default:
|
|
goto unknown;
|
|
}
|
|
|
|
return config0 & MIPS_CONF_M;
|
|
|
|
unknown:
|
|
panic(unknown_isa, config0);
|
|
}
|
|
|
|
static inline unsigned int decode_config1(struct cpuinfo_mips *c)
|
|
{
|
|
unsigned int config1;
|
|
|
|
config1 = read_c0_config1();
|
|
|
|
if (config1 & MIPS_CONF1_MD)
|
|
c->ases |= MIPS_ASE_MDMX;
|
|
if (config1 & MIPS_CONF1_WR)
|
|
c->options |= MIPS_CPU_WATCH;
|
|
if (config1 & MIPS_CONF1_CA)
|
|
c->ases |= MIPS_ASE_MIPS16;
|
|
if (config1 & MIPS_CONF1_EP)
|
|
c->options |= MIPS_CPU_EJTAG;
|
|
if (config1 & MIPS_CONF1_FP) {
|
|
c->options |= MIPS_CPU_FPU;
|
|
c->options |= MIPS_CPU_32FPR;
|
|
}
|
|
if (cpu_has_tlb)
|
|
c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
|
|
|
|
return config1 & MIPS_CONF_M;
|
|
}
|
|
|
|
static inline unsigned int decode_config2(struct cpuinfo_mips *c)
|
|
{
|
|
unsigned int config2;
|
|
|
|
config2 = read_c0_config2();
|
|
|
|
if (config2 & MIPS_CONF2_SL)
|
|
c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
|
|
|
|
return config2 & MIPS_CONF_M;
|
|
}
|
|
|
|
static inline unsigned int decode_config3(struct cpuinfo_mips *c)
|
|
{
|
|
unsigned int config3;
|
|
|
|
config3 = read_c0_config3();
|
|
|
|
if (config3 & MIPS_CONF3_SM)
|
|
c->ases |= MIPS_ASE_SMARTMIPS;
|
|
if (config3 & MIPS_CONF3_DSP)
|
|
c->ases |= MIPS_ASE_DSP;
|
|
if (config3 & MIPS_CONF3_VINT)
|
|
c->options |= MIPS_CPU_VINT;
|
|
if (config3 & MIPS_CONF3_VEIC)
|
|
c->options |= MIPS_CPU_VEIC;
|
|
if (config3 & MIPS_CONF3_MT)
|
|
c->ases |= MIPS_ASE_MIPSMT;
|
|
|
|
return config3 & MIPS_CONF_M;
|
|
}
|
|
|
|
static void __init decode_configs(struct cpuinfo_mips *c)
|
|
{
|
|
/* MIPS32 or MIPS64 compliant CPU. */
|
|
c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
|
|
MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
|
|
|
|
c->scache.flags = MIPS_CACHE_NOT_PRESENT;
|
|
|
|
/* Read Config registers. */
|
|
if (!decode_config0(c))
|
|
return; /* actually worth a panic() */
|
|
if (!decode_config1(c))
|
|
return;
|
|
if (!decode_config2(c))
|
|
return;
|
|
if (!decode_config3(c))
|
|
return;
|
|
}
|
|
|
|
static inline void cpu_probe_mips(struct cpuinfo_mips *c)
|
|
{
|
|
decode_configs(c);
|
|
switch (c->processor_id & 0xff00) {
|
|
case PRID_IMP_4KC:
|
|
c->cputype = CPU_4KC;
|
|
break;
|
|
case PRID_IMP_4KEC:
|
|
c->cputype = CPU_4KEC;
|
|
break;
|
|
case PRID_IMP_4KECR2:
|
|
c->cputype = CPU_4KEC;
|
|
break;
|
|
case PRID_IMP_4KSC:
|
|
case PRID_IMP_4KSD:
|
|
c->cputype = CPU_4KSC;
|
|
break;
|
|
case PRID_IMP_5KC:
|
|
c->cputype = CPU_5KC;
|
|
break;
|
|
case PRID_IMP_20KC:
|
|
c->cputype = CPU_20KC;
|
|
break;
|
|
case PRID_IMP_24K:
|
|
case PRID_IMP_24KE:
|
|
c->cputype = CPU_24K;
|
|
break;
|
|
case PRID_IMP_25KF:
|
|
c->cputype = CPU_25KF;
|
|
break;
|
|
case PRID_IMP_34K:
|
|
c->cputype = CPU_34K;
|
|
break;
|
|
case PRID_IMP_74K:
|
|
c->cputype = CPU_74K;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
|
|
{
|
|
decode_configs(c);
|
|
switch (c->processor_id & 0xff00) {
|
|
case PRID_IMP_AU1_REV1:
|
|
case PRID_IMP_AU1_REV2:
|
|
switch ((c->processor_id >> 24) & 0xff) {
|
|
case 0:
|
|
c->cputype = CPU_AU1000;
|
|
break;
|
|
case 1:
|
|
c->cputype = CPU_AU1500;
|
|
break;
|
|
case 2:
|
|
c->cputype = CPU_AU1100;
|
|
break;
|
|
case 3:
|
|
c->cputype = CPU_AU1550;
|
|
break;
|
|
case 4:
|
|
c->cputype = CPU_AU1200;
|
|
break;
|
|
default:
|
|
panic("Unknown Au Core!");
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
|
|
{
|
|
decode_configs(c);
|
|
|
|
/*
|
|
* For historical reasons the SB1 comes with it's own variant of
|
|
* cache code which eventually will be folded into c-r4k.c. Until
|
|
* then we pretend it's got it's own cache architecture.
|
|
*/
|
|
c->options &= ~MIPS_CPU_4K_CACHE;
|
|
c->options |= MIPS_CPU_SB1_CACHE;
|
|
|
|
switch (c->processor_id & 0xff00) {
|
|
case PRID_IMP_SB1:
|
|
c->cputype = CPU_SB1;
|
|
/* FPU in pass1 is known to have issues. */
|
|
if ((c->processor_id & 0xff) < 0x02)
|
|
c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
|
|
break;
|
|
case PRID_IMP_SB1A:
|
|
c->cputype = CPU_SB1A;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
|
|
{
|
|
decode_configs(c);
|
|
switch (c->processor_id & 0xff00) {
|
|
case PRID_IMP_SR71000:
|
|
c->cputype = CPU_SR71000;
|
|
c->scache.ways = 8;
|
|
c->tlbsize = 64;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static inline void cpu_probe_philips(struct cpuinfo_mips *c)
|
|
{
|
|
decode_configs(c);
|
|
switch (c->processor_id & 0xff00) {
|
|
case PRID_IMP_PR4450:
|
|
c->cputype = CPU_PR4450;
|
|
c->isa_level = MIPS_CPU_ISA_M32R1;
|
|
break;
|
|
default:
|
|
panic("Unknown Philips Core!"); /* REVISIT: die? */
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
__init void cpu_probe(void)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
|
|
c->processor_id = PRID_IMP_UNKNOWN;
|
|
c->fpu_id = FPIR_IMP_NONE;
|
|
c->cputype = CPU_UNKNOWN;
|
|
|
|
c->processor_id = read_c0_prid();
|
|
switch (c->processor_id & 0xff0000) {
|
|
case PRID_COMP_LEGACY:
|
|
cpu_probe_legacy(c);
|
|
break;
|
|
case PRID_COMP_MIPS:
|
|
cpu_probe_mips(c);
|
|
break;
|
|
case PRID_COMP_ALCHEMY:
|
|
cpu_probe_alchemy(c);
|
|
break;
|
|
case PRID_COMP_SIBYTE:
|
|
cpu_probe_sibyte(c);
|
|
break;
|
|
case PRID_COMP_SANDCRAFT:
|
|
cpu_probe_sandcraft(c);
|
|
break;
|
|
case PRID_COMP_PHILIPS:
|
|
cpu_probe_philips(c);
|
|
break;
|
|
default:
|
|
c->cputype = CPU_UNKNOWN;
|
|
}
|
|
if (c->options & MIPS_CPU_FPU) {
|
|
c->fpu_id = cpu_get_fpu_id();
|
|
|
|
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
|
|
c->isa_level == MIPS_CPU_ISA_M32R2 ||
|
|
c->isa_level == MIPS_CPU_ISA_M64R1 ||
|
|
c->isa_level == MIPS_CPU_ISA_M64R2) {
|
|
if (c->fpu_id & MIPS_FPIR_3D)
|
|
c->ases |= MIPS_ASE_MIPS3D;
|
|
}
|
|
}
|
|
}
|
|
|
|
__init void cpu_report(void)
|
|
{
|
|
struct cpuinfo_mips *c = ¤t_cpu_data;
|
|
|
|
printk("CPU revision is: %08x\n", c->processor_id);
|
|
if (c->options & MIPS_CPU_FPU)
|
|
printk("FPU revision is: %08x\n", c->fpu_id);
|
|
}
|