forked from luck/tmp_suning_uos_patched
4b550488f8
Hard to follow who is pointing what to where and why so it's simply getting in the way of the time code renovation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
304 lines
8.9 KiB
C
304 lines
8.9 KiB
C
/*
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* Copyright (C) 2004, 2005 by Basler Vision Technologies AG
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* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
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* Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
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* Manish Lachwani.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/tty.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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#include <linux/ioport.h>
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#include <linux/spinlock.h>
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#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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#include <asm/pgtable-32.h>
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#include <asm/io.h>
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#include <asm/time.h>
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#include <asm/rm9k-ocd.h>
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#include <excite.h>
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#define TITAN_UART_CLK 25000000
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#if 1
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/* normal serial port assignment */
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#define REGBASE_SER0 0x0208
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#define REGBASE_SER1 0x0238
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#define MASK_SER0 0x1
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#define MASK_SER1 0x2
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#else
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/* serial ports swapped */
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#define REGBASE_SER0 0x0238
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#define REGBASE_SER1 0x0208
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#define MASK_SER0 0x2
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#define MASK_SER1 0x1
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#endif
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unsigned long memsize;
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char modetty[30];
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unsigned int titan_irq = TITAN_IRQ;
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static void __iomem * ctl_regs;
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u32 unit_id;
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volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
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volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
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/* Protect access to shared GPI registers */
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DEFINE_SPINLOCK(titan_lock);
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int titan_irqflags;
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void __init plat_time_init(void)
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{
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const u32 modebit5 = ocd_readl(0x00e4);
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unsigned int
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mult = ((modebit5 >> 11) & 0x1f) + 2,
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div = ((modebit5 >> 16) & 0x1f) + 2;
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if (div == 33) div = 1;
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mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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/* The eXcite platform uses the alternate timer interrupt */
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set_c0_intcontrol(0x80);
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setup_irq(TIMER_IRQ, irq);
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}
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static int __init excite_init_console(void)
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{
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#if defined(CONFIG_SERIAL_8250)
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static __initdata char serr[] =
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KERN_ERR "Serial port #%u setup failed\n";
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struct uart_port up;
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/* Take the DUART out of reset */
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titan_writel(0x00ff1cff, CPRR);
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#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
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/* Enable both ports */
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titan_writel(MASK_SER0 | MASK_SER1, UACFG);
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#else
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/* Enable port #0 only */
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titan_writel(MASK_SER0, UACFG);
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#endif /* defined(CONFIG_KGDB) */
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/*
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* Set up serial port #0. Do not use autodetection; the result is
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* not what we want.
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*/
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memset(&up, 0, sizeof(up));
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up.membase = (char *) titan_addr(REGBASE_SER0);
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up.irq = TITAN_IRQ;
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up.uartclk = TITAN_UART_CLK;
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up.regshift = 0;
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up.iotype = UPIO_RM9000;
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up.type = PORT_RM9000;
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up.flags = UPF_SHARE_IRQ;
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up.line = 0;
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if (early_serial_setup(&up))
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printk(serr, up.line);
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#if CONFIG_SERIAL_8250_NR_UARTS > 1
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/* And now for port #1. */
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up.membase = (char *) titan_addr(REGBASE_SER1);
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up.line = 1;
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if (early_serial_setup(&up))
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printk(serr, up.line);
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#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
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#else
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/* Leave the DUART in reset */
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titan_writel(0x00ff3cff, CPRR);
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#endif /* defined(CONFIG_SERIAL_8250) */
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return 0;
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}
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static int __init excite_platform_init(void)
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{
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unsigned int i;
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unsigned char buf[3];
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u8 reg;
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void __iomem * dpr;
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/* BIU buffer allocations */
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ocd_writel(8, CPURSLMT); /* CPU */
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titan_writel(4, CPGRWL); /* GPI / Ethernet */
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/* Map control registers located in FPGA */
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ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
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if (!ctl_regs)
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panic("eXcite: failed to map platform control registers\n");
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memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
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unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
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/* Clear the reboot flag */
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dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
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reg = __raw_readb(dpr);
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__raw_writeb(reg & 0x7f, dpr);
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iounmap(dpr);
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/* Interrupt controller setup */
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for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
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ocd_writel(0x00000000, i + 0x04);
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ocd_writel(0xffffffff, i + 0x0c);
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}
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ocd_writel(0x2, NMICONFIG);
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ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
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INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
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ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
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| ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
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INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
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ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
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| ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
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INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
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ocd_writel((0x1 << (PHY_MSGINT % 0x20))
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| ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
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INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
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#if USB_IRQ < 10
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ocd_writel((0x1 << (USB_MSGINT % 0x20))
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| ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
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INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
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#endif
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/* Enable the packet FIFO, XDMA and XDMA arbiter */
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titan_writel(0x00ff18ff, CPRR);
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/*
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* Set up the PADMUX. Power down all ethernet slices,
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* they will be powered up and configured at device startup.
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*/
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titan_writel(0x00878206, CPTC1R);
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titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
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/* Reset and enable the FIFO block */
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titan_writel(0x00000001, SDRXFCIE);
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titan_writel(0x00000001, SDTXFCIE);
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titan_writel(0x00000100, SDRXFCIE);
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titan_writel(0x00000000, SDTXFCIE);
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/*
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* Initialize the common interrupt shared by all components of
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* the GPI/Ethernet subsystem.
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*/
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titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
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titan_writel(TITAN_MSGINT, CPCFG1);
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/*
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* XDMA configuration.
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* In order for the XDMA to be sharable among multiple drivers,
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* the setup must be done here in the platform. The reason is that
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* this setup can only be done while the XDMA is in reset. If this
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* were done in a driver, it would interrupt all other drivers
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* using the XDMA.
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*/
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titan_writel(0x80021dff, GXCFG); /* XDMA reset */
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titan_writel(0x00000000, CPXCISRA);
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titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
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#if defined (CONFIG_HIGHMEM)
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# error change for HIGHMEM support!
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#else
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titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
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#endif
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titan_writel(0, GXDMA_DESCADR);
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for (i = 0x5040; i <= 0x5300; i += 0x0040)
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titan_writel(0x80080000, i); /* reset channel */
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titan_writel((0x1 << 29) /* no sparse tx descr. */
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| (0x1 << 28) /* no sparse rx descr. */
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| (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
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| (0x1 << 21) | (0x1 << 22) /* data coherency */
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| (0x1 << 17)
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| 0x1dff,
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GXCFG);
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#if defined(CONFIG_SMP)
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# error No SMP support
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#else
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/* All interrupts go to core #0 only. */
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titan_writel(0x1f007fff, CPDST0A);
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titan_writel(0x00000000, CPDST0B);
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titan_writel(0x0000ff3f, CPDST1A);
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titan_writel(0x00000000, CPDST1B);
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titan_writel(0x00ffffff, CPXDSTA);
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titan_writel(0x00000000, CPXDSTB);
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#endif
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/* Enable DUART interrupts, disable everything else. */
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titan_writel(0x04000000, CPGIG0ER);
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titan_writel(0x000000c0, CPGIG1ER);
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excite_procfs_init();
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return 0;
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}
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void __init plat_mem_setup(void)
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{
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volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
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/* Announce RAM to system */
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add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
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/* Set up the peripheral address map */
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*(boot_ocd_base + (LKB9 / sizeof (u32))) = 0;
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*(boot_ocd_base + (LKB10 / sizeof (u32))) = 0;
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*(boot_ocd_base + (LKB11 / sizeof (u32))) = 0;
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*(boot_ocd_base + (LKB12 / sizeof (u32))) = 0;
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wmb();
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*(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4;
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wmb();
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ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
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ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
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ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
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ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
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/* Local bus slot #0 */
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ocd_writel(0x00040510, LDP0);
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ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
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ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
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/* Local bus slot #2 */
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ocd_writel(0x00000330, LDP2);
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ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
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ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
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/* Local bus slot #3 */
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ocd_writel(0x00123413, LDP3);
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ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
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ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
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}
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console_initcall(excite_init_console);
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arch_initcall(excite_platform_init);
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EXPORT_SYMBOL(titan_lock);
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EXPORT_SYMBOL(titan_irqflags);
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EXPORT_SYMBOL(titan_irq);
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EXPORT_SYMBOL(ocd_base);
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EXPORT_SYMBOL(titan_base);
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