Paul Cercueil 070e386727 clk: ingenic: Fix divider calculation with div tables ... commit 11a163f2c7d6a9f27ce144cd7e367a81c851621a upstream. The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an invalid assumption when a divider table is provided for the clock. Perfect example of this is the PLL0_HALF clock, which applies a /2 divider with the hardware value 0, and a /1 divider otherwise. Fixes: a9fa2893fc ("clk: ingenic: Add support for divider tables") Cc: <stable@vger.kernel.org> # 5.2 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2020-12-30 11:54:25 +01:00
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cgu.c	clk: ingenic: Fix divider calculation with div tables	2020-12-30 11:54:25 +01:00
cgu.h
jz4725b-cgu.c
jz4740-cgu.c
jz4770-cgu.c
jz4780-cgu.c	clk: JZ4780: Reformat the code to align it.	2020-07-27 18:18:14 -07:00
Kconfig
Makefile
pm.c
pm.h
tcu.c
x1000-cgu.c	clk: X1000: Add support for calculat REFCLK of USB PHY.	2020-07-27 18:18:14 -07:00
x1830-cgu.c