forked from luck/tmp_suning_uos_patched
1d3bb99648
Based on BenH's earlier work, this is a new version of the EMAC driver for the built-in ethernet found on PowerPC 4xx embedded CPUs. The same ASIC is also found in the Axon bridge chip. This new version is designed to work in the arch/powerpc tree, using the device tree to probe the device, rather than the old and ugly arch/ppc OCP layer. This driver is designed to sit alongside the old driver (that lies in drivers/net/ibm_emac and this one in drivers/net/ibm_newemac). The old driver is left in place to support arch/ppc until arch/ppc itself reaches its final demise (not too long now, with luck). This driver still has a number of things that could do with cleaning up, but I think they can be fixed up after merging. Specifically: - Should be adjusted to properly use the dma mapping API. Axon needs this. - Probe logic needs reworking, in conjuction with the general probing code for of_platform devices. The dependencies here between EMAC, MAL, ZMII etc. make this complicated. At present, it usually works, because we initialize and register the sub-drivers before the EMAC driver itself, and (being in driver code) runs after the devices themselves have been instantiated from the device tree. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Jeff Garzik <jeff@garzik.org>
91 lines
2.2 KiB
Plaintext
91 lines
2.2 KiB
Plaintext
config PPC_CELL
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bool
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default n
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config PPC_CELL_NATIVE
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bool
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select PPC_CELL
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select PPC_DCR_MMIO
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select PPC_OF_PLATFORM_PCI
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select PPC_INDIRECT_IO
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select PPC_NATIVE
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select MPIC
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select IBM_NEW_EMAC_EMAC4
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select IBM_NEW_EMAC_RGMII
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select IBM_NEW_EMAC_ZMII #test only
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select IBM_NEW_EMAC_TAH #test only
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default n
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config PPC_IBM_CELL_BLADE
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bool "IBM Cell Blade"
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depends on PPC_MULTIPLATFORM && PPC64
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select PPC_CELL_NATIVE
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select PPC_RTAS
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select MMIO_NVRAM
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select PPC_UDBG_16550
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select UDBG_RTAS_CONSOLE
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menu "Cell Broadband Engine options"
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depends on PPC_CELL
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config SPU_FS
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tristate "SPU file system"
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default m
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depends on PPC_CELL
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select SPU_BASE
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select MEMORY_HOTPLUG
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help
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The SPU file system is used to access Synergistic Processing
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Units on machines implementing the Broadband Processor
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Architecture.
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config SPU_FS_64K_LS
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bool "Use 64K pages to map SPE local store"
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# we depend on PPC_MM_SLICES for now rather than selecting
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# it because we depend on hugetlbfs hooks being present. We
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# will fix that when the generic code has been improved to
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# not require hijacking hugetlbfs hooks.
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depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
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default y
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select PPC_HAS_HASH_64K
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help
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This option causes SPE local stores to be mapped in process
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address spaces using 64K pages while the rest of the kernel
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uses 4K pages. This can improve performances of applications
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using multiple SPEs by lowering the TLB pressure on them.
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config SPU_BASE
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bool
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default n
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config CBE_RAS
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bool "RAS features for bare metal Cell BE"
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depends on PPC_CELL_NATIVE
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default y
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config CBE_THERM
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tristate "CBE thermal support"
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default m
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depends on CBE_RAS
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config CBE_CPUFREQ
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tristate "CBE frequency scaling"
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depends on CBE_RAS && CPU_FREQ
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default m
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help
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This adds the cpufreq driver for Cell BE processors.
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For details, take a look at <file:Documentation/cpu-freq/>.
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If you don't have such processor, say N
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config CBE_CPUFREQ_PMI
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tristate "CBE frequency scaling using PMI interface"
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depends on CBE_CPUFREQ && PPC_PMI && EXPERIMENTAL
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default n
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help
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Select this, if you want to use the PMI interface
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to switch frequencies. Using PMI, the
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processor will not only be able to run at lower speed,
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but also at lower core voltage.
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endmenu
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