Padmavathi Venna 3075741417 spi/s3c64xx: Bug fix for SPI with different FIFO level ... The existing macro fails for following scenarios. 1) S5P64X0 channel 1 2) S5PV210 channel 1 The FIFO data level supported in the above SoCs either 64 or 256 bytes depending on the channel. Because of this the TX_DONE is the 25 bit in the status register. The existing macro works for the following scenarios 1) S3C6410 all channels 2) S5PC100 all channels The FIFO data level supported in the above SoCs 64 bytes on all the channels. Because of this the TX_DONE is the 21 bit in the status register. So when we use the existing macro for the non-working SoCs it is not anding with the TX_DONE bit for transmission status check. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>		2011-07-06 15:03:08 +09:00
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amba-pl022.c
ath79_spi.c
atmel_spi.c
atmel_spi.h
au1550_spi.c
coldfire_qspi.c
davinci_spi.c
dw_spi_mid.c
dw_spi_mmio.c
dw_spi_pci.c
dw_spi.c
dw_spi.h
ep93xx_spi.c
Kconfig
Makefile
mpc52xx_psc_spi.c
mpc52xx_spi.c
mpc512x_psc_spi.c
omap_spi_100k.c
omap_uwire.c
omap2_mcspi.c
orion_spi.c
pxa2xx_spi_pci.c
pxa2xx_spi.c
spi_altera.c
spi_bfin_sport.c
spi_bfin5xx.c
spi_bitbang_txrx.h
spi_bitbang.c
spi_butterfly.c
spi_fsl_espi.c
spi_fsl_lib.c
spi_fsl_lib.h
spi_fsl_spi.c
spi_gpio.c
spi_imx.c
spi_lm70llp.c
spi_nuc900.c
spi_oc_tiny.c
spi_ppc4xx.c
spi_s3c24xx_fiq.h
spi_s3c24xx_fiq.S
spi_s3c24xx_gpio.c
spi_s3c24xx.c
spi_s3c64xx.c
spi_sh_msiof.c
spi_sh_sci.c
spi_sh.c
spi_stmp.c
spi_tegra.c
spi_topcliff_pch.c
spi_txx9.c
spi.c
spidev.c
ti-ssp-spi.c
tle62x0.c
xilinx_spi.c