forked from luck/tmp_suning_uos_patched
ef559def40
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
157 lines
3.5 KiB
C
157 lines
3.5 KiB
C
/*
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* linux/arch/arm/mach-mmp/aspenite.c
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*
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* Support for the Marvell PXA168-based Aspenite and Zylonite2
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* Development Platform.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/smc91x.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/addr-map.h>
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#include <mach/mfp-pxa168.h>
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#include <mach/pxa168.h>
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#include <mach/gpio.h>
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#include "common.h"
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static unsigned long common_pin_config[] __initdata = {
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/* Data Flash Interface */
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GPIO0_DFI_D15,
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GPIO1_DFI_D14,
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GPIO2_DFI_D13,
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GPIO3_DFI_D12,
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GPIO4_DFI_D11,
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GPIO5_DFI_D10,
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GPIO6_DFI_D9,
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GPIO7_DFI_D8,
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GPIO8_DFI_D7,
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GPIO9_DFI_D6,
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GPIO10_DFI_D5,
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GPIO11_DFI_D4,
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GPIO12_DFI_D3,
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GPIO13_DFI_D2,
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GPIO14_DFI_D1,
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GPIO15_DFI_D0,
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/* Static Memory Controller */
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GPIO18_SMC_nCS0,
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GPIO34_SMC_nCS1,
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GPIO23_SMC_nLUA,
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GPIO25_SMC_nLLA,
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GPIO28_SMC_RDY,
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GPIO29_SMC_SCLK,
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GPIO35_SMC_BE1,
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GPIO36_SMC_BE2,
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GPIO27_GPIO, /* Ethernet IRQ */
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/* UART1 */
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GPIO107_UART1_RXD,
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GPIO108_UART1_TXD,
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};
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static struct smc91x_platdata smc91x_info = {
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.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
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};
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = SMC_CS1_PHYS_BASE + 0x300,
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.end = SMC_CS1_PHYS_BASE + 0xfffff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gpio_to_irq(27),
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.end = gpio_to_irq(27),
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
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}
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.dev = {
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.platform_data = &smc91x_info,
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},
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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static struct mtd_partition aspenite_nand_partitions[] = {
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{
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.name = "bootloader",
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.offset = 0,
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.size = SZ_1M,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "reserved",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_128K,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "reserved",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_8M,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = (SZ_2M + SZ_1M),
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.mask_flags = 0,
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}, {
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.name = "filesystem",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_48M,
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.mask_flags = 0,
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}
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};
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static struct pxa3xx_nand_platform_data aspenite_nand_info = {
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.enable_arbiter = 1,
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.parts = aspenite_nand_partitions,
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.nr_parts = ARRAY_SIZE(aspenite_nand_partitions),
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};
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static void __init common_init(void)
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{
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mfp_config(ARRAY_AND_SIZE(common_pin_config));
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/* on-chip devices */
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pxa168_add_uart(1);
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pxa168_add_nand(&aspenite_nand_info);
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/* off-chip devices */
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platform_device_register(&smc91x_device);
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}
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MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
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.phys_io = APB_PHYS_BASE,
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.boot_params = 0x00000100,
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.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
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.map_io = pxa_map_io,
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.init_irq = pxa168_init_irq,
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.timer = &pxa168_timer,
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.init_machine = common_init,
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MACHINE_END
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MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
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.phys_io = APB_PHYS_BASE,
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.boot_params = 0x00000100,
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.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
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.map_io = pxa_map_io,
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.init_irq = pxa168_init_irq,
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.timer = &pxa168_timer,
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.init_machine = common_init,
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MACHINE_END
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