forked from luck/tmp_suning_uos_patched
5a846abad0
At the CPU/ISA level, the J2 is compatible with SH-2, and thus the changes to add J2 support build on existing SH-2 support. However, J2 does not duplicate the memory-mapped SH-2 features like the cache interface. Instead, the cache interfaces is described in the device tree, and new code is added to be able to access the flat device tree at early boot before it is unflattened. Support is also added for receiving interrupts on trap numbers in the range 16 to 31, since the J-Core aic1 interrupt controller generates these traps. This range was unused but nominally for hardware exceptions on SH-2, and a few values in this range were used for exceptions on SH-2A, but SH-2A has its own version of the relevant code. No individual cpu subtypes are added for J2 since the intent moving forward is to represent SoCs with device tree rather than as hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item exists only to fit into the existing cpu selection mechanism until it is overhauled. Signed-off-by: Rich Felker <dalias@libc.org>
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
/*
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* arch/sh/mm/cache-j2.c
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*
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* Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
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*
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* Released under the terms of the GNU GPL v2.0.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/cpumask.h>
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#include <asm/cache.h>
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#include <asm/addrspace.h>
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#include <asm/processor.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
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#define ICACHE_ENABLE 0x1
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#define DCACHE_ENABLE 0x2
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#define CACHE_ENABLE (ICACHE_ENABLE | DCACHE_ENABLE)
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#define ICACHE_FLUSH 0x100
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#define DCACHE_FLUSH 0x200
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#define CACHE_FLUSH (ICACHE_FLUSH | DCACHE_FLUSH)
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u32 __iomem *j2_ccr_base;
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static void j2_flush_icache(void *args)
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{
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unsigned cpu;
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for_each_possible_cpu(cpu)
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__raw_writel(CACHE_ENABLE | ICACHE_FLUSH, j2_ccr_base + cpu);
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}
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static void j2_flush_dcache(void *args)
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{
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unsigned cpu;
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for_each_possible_cpu(cpu)
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__raw_writel(CACHE_ENABLE | DCACHE_FLUSH, j2_ccr_base + cpu);
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}
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static void j2_flush_both(void *args)
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{
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unsigned cpu;
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for_each_possible_cpu(cpu)
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__raw_writel(CACHE_ENABLE | CACHE_FLUSH, j2_ccr_base + cpu);
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}
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void __init j2_cache_init(void)
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{
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if (!j2_ccr_base)
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return;
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local_flush_cache_all = j2_flush_both;
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local_flush_cache_mm = j2_flush_both;
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local_flush_cache_dup_mm = j2_flush_both;
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local_flush_cache_page = j2_flush_both;
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local_flush_cache_range = j2_flush_both;
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local_flush_dcache_page = j2_flush_dcache;
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local_flush_icache_range = j2_flush_icache;
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local_flush_icache_page = j2_flush_icache;
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local_flush_cache_sigtramp = j2_flush_icache;
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pr_info("Initial J2 CCR is %.8x\n", __raw_readl(j2_ccr_base));
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}
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