forked from luck/tmp_suning_uos_patched
9918cda523
Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
136 lines
4.2 KiB
C
136 lines
4.2 KiB
C
/*
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* include/asm-arm/arch-ns9xxx/regs-mem.h
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*
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* Copyright (C) 2006 by Digi International Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGSMEM_H
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#define __ASM_ARCH_REGSMEM_H
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#include <asm/hardware.h>
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/* Memory Module */
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/* Control register */
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#define MEM_CTRL __REG(0xa0700000)
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/* Status register */
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#define MEM_STAT __REG(0xa0700004)
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/* Configuration register */
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#define MEM_CONF __REG(0xa0700008)
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/* Dynamic Memory Control register */
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#define MEM_DMCTRL __REG(0xa0700020)
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/* Dynamic Memory Refresh Timer */
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#define MEM_DMRT __REG(0xa0700024)
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/* Dynamic Memory Read Configuration register */
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#define MEM_DMRC __REG(0xa0700028)
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/* Dynamic Memory Precharge Command Period (tRP) */
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#define MEM_DMPCP __REG(0xa0700030)
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/* Dynamic Memory Active to Precharge Command Period (tRAS) */
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#define MEM_DMAPCP __REG(0xa0700034)
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/* Dynamic Memory Self-Refresh Exit Time (tSREX) */
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#define MEM_DMSRET __REG(0xa0700038)
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/* Dynamic Memory Last Data Out to Active Time (tAPR) */
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#define MEM_DMLDOAT __REG(0xa070003c)
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/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
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#define MEM_DMDIACT __REG(0xa0700040)
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/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
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#define MEM_DMWRT __REG(0xa0700044)
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/* Dynamic Memory Active to Active Command Period (tRC) */
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#define MEM_DMAACP __REG(0xa0700048)
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/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */
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#define MEM_DMARP __REG(0xa070004c)
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/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
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#define MEM_DMESRAC __REG(0xa0700050)
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/* Dynamic Memory Active Bank A to Active B Time (tRRD) */
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#define MEM_DMABAABT __REG(0xa0700054)
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/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
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#define MEM_DMLMACT __REG(0xa0700058)
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/* Static Memory Extended Wait */
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#define MEM_SMEW __REG(0xa0700080)
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/* Dynamic Memory Configuration Register x */
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#define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3)
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/* Dynamic Memory RAS and CAS Delay x */
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#define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3)
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/* Static Memory Configuration Register x */
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#define MEM_SMC(x) __REG2(0xa0700200, (x) << 3)
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/* Static Memory Configuration Register x: Write protect */
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#define MEM_SMC_WSMC __REGBIT(20)
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#define MEM_SMC_WSMC_OFF __REGVAL(MEM_SMC_WSMC, 0)
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#define MEM_SMC_WSMC_ON __REGVAL(MEM_SMC_WSMC, 1)
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/* Static Memory Configuration Register x: Buffer enable */
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#define MEM_SMC_BSMC __REGBIT(19)
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#define MEM_SMC_BSMC_OFF __REGVAL(MEM_SMC_BSMC, 0)
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#define MEM_SMC_BSMC_ON __REGVAL(MEM_SMC_BSMC, 1)
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/* Static Memory Configuration Register x: Extended Wait */
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#define MEM_SMC_EW __REGBIT(8)
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#define MEM_SMC_EW_OFF __REGVAL(MEM_SMC_EW, 0)
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#define MEM_SMC_EW_ON __REGVAL(MEM_SMC_EW, 1)
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/* Static Memory Configuration Register x: Byte lane state */
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#define MEM_SMC_PB __REGBIT(7)
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#define MEM_SMC_PB_0 __REGVAL(MEM_SMC_PB, 0)
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#define MEM_SMC_PB_1 __REGVAL(MEM_SMC_PB, 1)
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/* Static Memory Configuration Register x: Chip select polarity */
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#define MEM_SMC_PC __REGBIT(6)
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#define MEM_SMC_PC_AL __REGVAL(MEM_SMC_PC, 0)
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#define MEM_SMC_PC_AH __REGVAL(MEM_SMC_PC, 1)
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/* static memory configuration register x: page mode*/
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#define MEM_SMC_PM __REGBIT(3)
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#define MEM_SMC_PM_DIS __REGVAL(MEM_SMC_PM, 0)
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#define MEM_SMC_PM_ASYNC __REGVAL(MEM_SMC_PM, 1)
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/* static memory configuration register x: Memory width */
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#define MEM_SMC_MW __REGBITS(1, 0)
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#define MEM_SMC_MW_8 __REGVAL(MEM_SMC_MW, 0)
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#define MEM_SMC_MW_16 __REGVAL(MEM_SMC_MW, 1)
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#define MEM_SMC_MW_32 __REGVAL(MEM_SMC_MW, 2)
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/* Static Memory Write Enable Delay x */
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#define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3)
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/* Static Memory Output Enable Delay x */
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#define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3)
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/* Static Memory Read Delay x */
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#define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3)
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/* Static Memory Page Mode Read Delay 0 */
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#define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3)
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/* Static Memory Write Delay */
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#define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3)
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/* Static Memory Turn Round Delay x */
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#define MEM_SWT(x) __REG2(0xa0700218, (x) << 3)
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#endif /* ifndef __ASM_ARCH_REGSMEM_H */
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