forked from luck/tmp_suning_uos_patched
c7111c1318
The problem we can't take advantage of lowest priority delivery mode if the vectors are allocated for only one cpu at a time. Nor can we work around hardware that assumes lowest priority delivery mode is always used with several cpus. So this patch introduces the concept of a vector_allocation_domain. A set of cpus that will receive an irq on the same vector. Currently the code for implementing this is placed in the genapic structure so we can vary this depending on how we are using the io_apics. This allows us to restore the previous behaviour of genapic_flat without removing the benefits of having separate vector allocation for large machines. This should also fix the problem report where a hyperthreaded cpu was receving the irq on the wrong hyperthread when in logical delivery mode because the previous behaviour is restored. This patch properly records our allocation of the first 16 irqs to the first 16 available vectors on all cpus. This should be fine but it may run into problems with multiple interrupts at the same interrupt level. Except for some badly maintained comments in the code and the behaviour of the interrupt allocator I have no real understanding of that problem. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
30 lines
968 B
C
30 lines
968 B
C
#ifndef __ASM_MACH_APIC_H
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#define __ASM_MACH_APIC_H
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/*
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* Copyright 2004 James Cleverdon, IBM.
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* Subject to the GNU Public License, v.2
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*
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* Generic APIC sub-arch defines.
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*
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* Hacked for x86-64 by James Cleverdon from i386 architecture code by
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* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
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* James Cleverdon.
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*/
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#include <asm/genapic.h>
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#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
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#define INT_DEST_MODE (genapic->int_dest_mode)
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#define TARGET_CPUS (genapic->target_cpus())
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#define vector_allocation_domain (genapic->vector_allocation_domain)
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#define apic_id_registered (genapic->apic_id_registered)
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#define init_apic_ldr (genapic->init_apic_ldr)
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#define send_IPI_mask (genapic->send_IPI_mask)
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#define send_IPI_allbutself (genapic->send_IPI_allbutself)
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#define send_IPI_all (genapic->send_IPI_all)
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#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
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#define phys_pkg_id (genapic->phys_pkg_id)
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#endif /* __ASM_MACH_APIC_H */
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