forked from luck/tmp_suning_uos_patched
56fb4df6da
UltraSPARC has special sets of global registers which are switched to for certain trap types. There is one set for MMU related traps, one set of Interrupt Vector processing, and another set (called the Alternate globals) for all other trap types. For what seems like forever we've hard coded the values in some of these trap registers. Some examples include: 1) Interrupt Vector global %g6 holds current processors interrupt work struct where received interrupts are managed for IRQ handler dispatch. 2) MMU global %g7 holds the base of the page tables of the currently active address space. 3) Alternate global %g6 held the current_thread_info() value. Such hardcoding has resulted in some serious issues in many areas. There are some code sequences where having another register available would help clean up the implementation. Taking traps such as cross-calls from the OBP firmware requires some trick code sequences wherein we have to save away and restore all of the special sets of global registers when we enter/exit OBP. We were also using the IMMU TSB register on SMP to hold the per-cpu area base address, which doesn't work any longer now that we actually use the TSB facility of the cpu. The implementation is pretty straight forward. One tricky bit is getting the current processor ID as that is different on different cpu variants. We use a stub with a fancy calling convention which we patch at boot time. The calling convention is that the stub is branched to and the (PC - 4) to return to is in register %g1. The cpu number is left in %g6. This stub can be invoked by using the __GET_CPUID macro. We use an array of per-cpu trap state to store the current thread and physical address of the current address space's page tables. The TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this table, it uses __GET_CPUID and also clobbers %g1. TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load the current processor's IRQ software state into %g6. It also uses __GET_CPUID and clobbers %g1. Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the current address space's page tables into %g7, it clobbers %g1 and uses __GET_CPUID. Many refinements are possible, as well as some tuning, with this stuff in place. Signed-off-by: David S. Miller <davem@davemloft.net>
257 lines
6.3 KiB
ArmAsm
257 lines
6.3 KiB
ArmAsm
/* $Id: etrap.S,v 1.46 2002/02/09 19:49:30 davem Exp $
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* etrap.S: Preparing for entry into the kernel on Sparc V9.
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*
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* Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <linux/config.h>
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#include <asm/asi.h>
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#include <asm/pstate.h>
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#include <asm/ptrace.h>
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#include <asm/page.h>
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#include <asm/spitfire.h>
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#include <asm/head.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
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#define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV)
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#define ETRAP_PSTATE2 \
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(PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
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/*
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* On entry, %g7 is return address - 0x4.
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* %g4 and %g5 will be preserved %l4 and %l5 respectively.
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*/
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.text
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.align 64
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.globl etrap, etrap_irq, etraptl1
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etrap: rdpr %pil, %g2
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etrap_irq:
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TRAP_LOAD_THREAD_REG
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rdpr %tstate, %g1
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sllx %g2, 20, %g3
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andcc %g1, TSTATE_PRIV, %g0
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or %g1, %g3, %g1
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bne,pn %xcc, 1f
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sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
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wrpr %g0, 7, %cleanwin
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sethi %hi(TASK_REGOFF), %g2
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sethi %hi(TSTATE_PEF), %g3
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or %g2, %lo(TASK_REGOFF), %g2
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and %g1, %g3, %g3
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brnz,pn %g3, 1f
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add %g6, %g2, %g2
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wr %g0, 0, %fprs
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1: rdpr %tpc, %g3
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stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
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rdpr %tnpc, %g1
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stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
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rd %y, %g3
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stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
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st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
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save %g2, -STACK_BIAS, %sp ! Ordering here is critical
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mov %g6, %l6
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bne,pn %xcc, 3f
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mov PRIMARY_CONTEXT, %l4
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rdpr %canrestore, %g3
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rdpr %wstate, %g2
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wrpr %g0, 0, %canrestore
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sll %g2, 3, %g2
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mov 1, %l5
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stb %l5, [%l6 + TI_FPDEPTH]
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wrpr %g3, 0, %otherwin
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wrpr %g2, 0, %wstate
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sethi %hi(sparc64_kern_pri_context), %g2
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ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
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stxa %g3, [%l4] ASI_DMMU
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flush %l6
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wr %g0, ASI_AIUS, %asi
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2: wrpr %g0, 0x0, %tl
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mov %g4, %l4
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mov %g5, %l5
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mov %g7, %l2
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wrpr %g0, ETRAP_PSTATE1, %pstate
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stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
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stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
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stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
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stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
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stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
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stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
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stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
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stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
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stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
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stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
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stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
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stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
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stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
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stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
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stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
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wrpr %g0, ETRAP_PSTATE2, %pstate
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mov %l6, %g6
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LOAD_PER_CPU_BASE(%g4, %g3)
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jmpl %l2 + 0x4, %g0
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ldx [%g6 + TI_TASK], %g4
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3: ldub [%l6 + TI_FPDEPTH], %l5
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add %l6, TI_FPSAVED + 1, %l4
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srl %l5, 1, %l3
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add %l5, 2, %l5
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stb %l5, [%l6 + TI_FPDEPTH]
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ba,pt %xcc, 2b
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stb %g0, [%l4 + %l3]
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nop
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etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
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* We place this right after pt_regs on the trap stack.
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* The layout is:
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* 0x00 TL1's TSTATE
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* 0x08 TL1's TPC
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* 0x10 TL1's TNPC
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* 0x18 TL1's TT
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* ...
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* 0x58 TL4's TT
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* 0x60 TL
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*/
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TRAP_LOAD_THREAD_REG
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sub %sp, ((4 * 8) * 4) + 8, %g2
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rdpr %tl, %g1
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wrpr %g0, 1, %tl
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rdpr %tstate, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x00]
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rdpr %tpc, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x08]
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rdpr %tnpc, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x10]
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rdpr %tt, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x18]
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wrpr %g0, 2, %tl
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rdpr %tstate, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x20]
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rdpr %tpc, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x28]
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rdpr %tnpc, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x30]
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rdpr %tt, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x38]
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wrpr %g0, 3, %tl
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rdpr %tstate, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x40]
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rdpr %tpc, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x48]
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rdpr %tnpc, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x50]
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rdpr %tt, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x58]
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wrpr %g0, 4, %tl
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rdpr %tstate, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x60]
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rdpr %tpc, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x68]
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rdpr %tnpc, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x70]
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rdpr %tt, %g3
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stx %g3, [%g2 + STACK_BIAS + 0x78]
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wrpr %g1, %tl
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stx %g1, [%g2 + STACK_BIAS + 0x80]
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rdpr %tstate, %g1
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sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
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ba,pt %xcc, 1b
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andcc %g1, TSTATE_PRIV, %g0
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.align 64
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.globl scetrap
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scetrap:
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TRAP_LOAD_THREAD_REG
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rdpr %pil, %g2
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rdpr %tstate, %g1
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sllx %g2, 20, %g3
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andcc %g1, TSTATE_PRIV, %g0
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or %g1, %g3, %g1
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bne,pn %xcc, 1f
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sub %sp, (STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS), %g2
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wrpr %g0, 7, %cleanwin
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sllx %g1, 51, %g3
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sethi %hi(TASK_REGOFF), %g2
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or %g2, %lo(TASK_REGOFF), %g2
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brlz,pn %g3, 1f
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add %g6, %g2, %g2
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wr %g0, 0, %fprs
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1: rdpr %tpc, %g3
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stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
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rdpr %tnpc, %g1
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stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
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stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
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save %g2, -STACK_BIAS, %sp ! Ordering here is critical
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mov %g6, %l6
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bne,pn %xcc, 2f
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mov ASI_P, %l7
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rdpr %canrestore, %g3
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rdpr %wstate, %g2
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wrpr %g0, 0, %canrestore
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sll %g2, 3, %g2
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mov PRIMARY_CONTEXT, %l4
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wrpr %g3, 0, %otherwin
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wrpr %g2, 0, %wstate
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sethi %hi(sparc64_kern_pri_context), %g2
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ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
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stxa %g3, [%l4] ASI_DMMU
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flush %l6
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mov ASI_AIUS, %l7
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2: mov %g4, %l4
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mov %g5, %l5
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add %g7, 0x4, %l2
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wrpr %g0, ETRAP_PSTATE1, %pstate
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stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
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stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
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sllx %l7, 24, %l7
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stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
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rdpr %cwp, %l0
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stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
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stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
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stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
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stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
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or %l7, %l0, %l7
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sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0
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or %l7, %l0, %l7
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wrpr %l2, %tnpc
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wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
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stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
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stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
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stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
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stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
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stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
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stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
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stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
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mov %l6, %g6
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stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
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LOAD_PER_CPU_BASE(%g4, %g3)
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ldx [%g6 + TI_TASK], %g4
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done
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#undef TASK_REGOFF
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#undef ETRAP_PSTATE1
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