forked from luck/tmp_suning_uos_patched
5808184f1b
This is needed for the fix of the M3 workaround. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
620 lines
15 KiB
C
620 lines
15 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* A small micro-assembler. It is intentionally kept simple, does only
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* support a subset of instructions, and does not try to hide pipeline
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* effects like branch delay slots.
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*
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* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
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* Copyright (C) 2005, 2007 Maciej W. Rozycki
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* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <asm/inst.h>
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#include <asm/elf.h>
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#include <asm/bugs.h>
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#include <asm/uasm.h>
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enum fields {
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RS = 0x001,
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RT = 0x002,
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RD = 0x004,
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RE = 0x008,
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SIMM = 0x010,
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UIMM = 0x020,
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BIMM = 0x040,
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JIMM = 0x080,
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FUNC = 0x100,
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SET = 0x200,
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SCIMM = 0x400
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};
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#define OP_MASK 0x3f
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#define OP_SH 26
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#define RS_MASK 0x1f
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#define RS_SH 21
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#define RT_MASK 0x1f
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#define RT_SH 16
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#define RD_MASK 0x1f
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#define RD_SH 11
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#define RE_MASK 0x1f
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#define RE_SH 6
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#define IMM_MASK 0xffff
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#define IMM_SH 0
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#define JIMM_MASK 0x3ffffff
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#define JIMM_SH 0
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#define FUNC_MASK 0x3f
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#define FUNC_SH 0
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#define SET_MASK 0x7
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#define SET_SH 0
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#define SCIMM_MASK 0xfffff
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#define SCIMM_SH 6
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enum opcode {
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insn_invalid,
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insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
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insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
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insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
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insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
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insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
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insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
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insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
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insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,
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insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
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insn_dins, insn_syscall
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};
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struct insn {
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enum opcode opcode;
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u32 match;
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enum fields fields;
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};
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/* This macro sets the non-variable bits of an instruction. */
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#define M(a, b, c, d, e, f) \
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((a) << OP_SH \
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| (b) << RS_SH \
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| (c) << RT_SH \
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| (d) << RD_SH \
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| (e) << RE_SH \
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| (f) << FUNC_SH)
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static struct insn insn_table[] __cpuinitdata = {
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{ insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
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{ insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
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{ insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
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{ insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
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{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
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{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
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{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
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{ insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
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{ insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
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{ insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
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{ insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
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{ insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
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{ insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
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{ insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
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{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
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{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
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{ insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
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{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
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{ insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
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{ insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
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{ insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
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{ insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
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{ insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
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{ insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
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{ insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
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{ insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
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{ insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
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{ insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
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{ insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
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{ insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
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{ insn_invalid, 0, 0 }
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};
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#undef M
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static inline __cpuinit u32 build_rs(u32 arg)
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{
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if (arg & ~RS_MASK)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return (arg & RS_MASK) << RS_SH;
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}
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static inline __cpuinit u32 build_rt(u32 arg)
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{
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if (arg & ~RT_MASK)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return (arg & RT_MASK) << RT_SH;
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}
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static inline __cpuinit u32 build_rd(u32 arg)
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{
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if (arg & ~RD_MASK)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return (arg & RD_MASK) << RD_SH;
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}
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static inline __cpuinit u32 build_re(u32 arg)
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{
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if (arg & ~RE_MASK)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return (arg & RE_MASK) << RE_SH;
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}
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static inline __cpuinit u32 build_simm(s32 arg)
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{
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if (arg > 0x7fff || arg < -0x8000)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return arg & 0xffff;
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}
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static inline __cpuinit u32 build_uimm(u32 arg)
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{
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if (arg & ~IMM_MASK)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return arg & IMM_MASK;
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}
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static inline __cpuinit u32 build_bimm(s32 arg)
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{
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if (arg > 0x1ffff || arg < -0x20000)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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if (arg & 0x3)
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printk(KERN_WARNING "Invalid micro-assembler branch target\n");
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return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
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}
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static inline __cpuinit u32 build_jimm(u32 arg)
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{
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if (arg & ~((JIMM_MASK) << 2))
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return (arg >> 2) & JIMM_MASK;
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}
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static inline __cpuinit u32 build_scimm(u32 arg)
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{
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if (arg & ~SCIMM_MASK)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return (arg & SCIMM_MASK) << SCIMM_SH;
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}
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static inline __cpuinit u32 build_func(u32 arg)
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{
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if (arg & ~FUNC_MASK)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return arg & FUNC_MASK;
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}
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static inline __cpuinit u32 build_set(u32 arg)
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{
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if (arg & ~SET_MASK)
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printk(KERN_WARNING "Micro-assembler field overflow\n");
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return arg & SET_MASK;
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}
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/*
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* The order of opcode arguments is implicitly left to right,
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* starting with RS and ending with FUNC or IMM.
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*/
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static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
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{
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struct insn *ip = NULL;
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unsigned int i;
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va_list ap;
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u32 op;
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for (i = 0; insn_table[i].opcode != insn_invalid; i++)
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if (insn_table[i].opcode == opc) {
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ip = &insn_table[i];
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break;
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}
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if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
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panic("Unsupported Micro-assembler instruction %d", opc);
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op = ip->match;
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va_start(ap, opc);
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if (ip->fields & RS)
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op |= build_rs(va_arg(ap, u32));
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if (ip->fields & RT)
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op |= build_rt(va_arg(ap, u32));
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if (ip->fields & RD)
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op |= build_rd(va_arg(ap, u32));
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if (ip->fields & RE)
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op |= build_re(va_arg(ap, u32));
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if (ip->fields & SIMM)
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op |= build_simm(va_arg(ap, s32));
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if (ip->fields & UIMM)
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op |= build_uimm(va_arg(ap, u32));
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if (ip->fields & BIMM)
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op |= build_bimm(va_arg(ap, s32));
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if (ip->fields & JIMM)
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op |= build_jimm(va_arg(ap, u32));
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if (ip->fields & FUNC)
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op |= build_func(va_arg(ap, u32));
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if (ip->fields & SET)
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op |= build_set(va_arg(ap, u32));
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if (ip->fields & SCIMM)
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op |= build_scimm(va_arg(ap, u32));
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va_end(ap);
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**buf = op;
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(*buf)++;
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}
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#define I_u1u2u3(op) \
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Ip_u1u2u3(op) \
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{ \
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build_insn(buf, insn##op, a, b, c); \
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}
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#define I_u2u1u3(op) \
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Ip_u2u1u3(op) \
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{ \
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build_insn(buf, insn##op, b, a, c); \
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}
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#define I_u3u1u2(op) \
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Ip_u3u1u2(op) \
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{ \
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build_insn(buf, insn##op, b, c, a); \
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}
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#define I_u1u2s3(op) \
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Ip_u1u2s3(op) \
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{ \
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build_insn(buf, insn##op, a, b, c); \
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}
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#define I_u2s3u1(op) \
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Ip_u2s3u1(op) \
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{ \
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build_insn(buf, insn##op, c, a, b); \
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}
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#define I_u2u1s3(op) \
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Ip_u2u1s3(op) \
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{ \
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build_insn(buf, insn##op, b, a, c); \
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}
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#define I_u2u1msbu3(op) \
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Ip_u2u1msbu3(op) \
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{ \
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build_insn(buf, insn##op, b, a, c+d-1, c); \
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}
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#define I_u1u2(op) \
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Ip_u1u2(op) \
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{ \
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build_insn(buf, insn##op, a, b); \
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}
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#define I_u1s2(op) \
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Ip_u1s2(op) \
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{ \
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build_insn(buf, insn##op, a, b); \
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}
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#define I_u1(op) \
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Ip_u1(op) \
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{ \
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build_insn(buf, insn##op, a); \
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}
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#define I_0(op) \
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Ip_0(op) \
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{ \
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build_insn(buf, insn##op); \
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}
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I_u2u1s3(_addiu)
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I_u3u1u2(_addu)
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I_u2u1u3(_andi)
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I_u3u1u2(_and)
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I_u1u2s3(_beq)
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I_u1u2s3(_beql)
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I_u1s2(_bgez)
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I_u1s2(_bgezl)
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I_u1s2(_bltz)
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I_u1s2(_bltzl)
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I_u1u2s3(_bne)
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I_u2s3u1(_cache)
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I_u1u2u3(_dmfc0)
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I_u1u2u3(_dmtc0)
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I_u2u1s3(_daddiu)
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I_u3u1u2(_daddu)
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I_u2u1u3(_dsll)
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I_u2u1u3(_dsll32)
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I_u2u1u3(_dsra)
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I_u2u1u3(_dsrl)
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I_u2u1u3(_dsrl32)
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I_u2u1u3(_drotr)
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I_u3u1u2(_dsubu)
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I_0(_eret)
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I_u1(_j)
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I_u1(_jal)
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I_u1(_jr)
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I_u2s3u1(_ld)
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I_u2s3u1(_ll)
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I_u2s3u1(_lld)
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I_u1s2(_lui)
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I_u2s3u1(_lw)
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I_u1u2u3(_mfc0)
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I_u1u2u3(_mtc0)
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I_u2u1u3(_ori)
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I_u3u1u2(_or)
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I_u2s3u1(_pref)
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I_0(_rfe)
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I_u2s3u1(_sc)
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I_u2s3u1(_scd)
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I_u2s3u1(_sd)
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I_u2u1u3(_sll)
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I_u2u1u3(_sra)
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I_u2u1u3(_srl)
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I_u2u1u3(_rotr)
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I_u3u1u2(_subu)
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I_u2s3u1(_sw)
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I_0(_tlbp)
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I_0(_tlbr)
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I_0(_tlbwi)
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I_0(_tlbwr)
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I_u3u1u2(_xor)
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I_u2u1u3(_xori)
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I_u2u1msbu3(_dins);
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I_u1(_syscall);
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/* Handle labels. */
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void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
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{
|
|
(*lab)->addr = addr;
|
|
(*lab)->lab = lid;
|
|
(*lab)++;
|
|
}
|
|
|
|
int __cpuinit uasm_in_compat_space_p(long addr)
|
|
{
|
|
/* Is this address in 32bit compat space? */
|
|
#ifdef CONFIG_64BIT
|
|
return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
|
|
#else
|
|
return 1;
|
|
#endif
|
|
}
|
|
|
|
static int __cpuinit uasm_rel_highest(long val)
|
|
{
|
|
#ifdef CONFIG_64BIT
|
|
return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
static int __cpuinit uasm_rel_higher(long val)
|
|
{
|
|
#ifdef CONFIG_64BIT
|
|
return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
int __cpuinit uasm_rel_hi(long val)
|
|
{
|
|
return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
|
|
}
|
|
|
|
int __cpuinit uasm_rel_lo(long val)
|
|
{
|
|
return ((val & 0xffff) ^ 0x8000) - 0x8000;
|
|
}
|
|
|
|
void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
|
|
{
|
|
if (!uasm_in_compat_space_p(addr)) {
|
|
uasm_i_lui(buf, rs, uasm_rel_highest(addr));
|
|
if (uasm_rel_higher(addr))
|
|
uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
|
|
if (uasm_rel_hi(addr)) {
|
|
uasm_i_dsll(buf, rs, rs, 16);
|
|
uasm_i_daddiu(buf, rs, rs, uasm_rel_hi(addr));
|
|
uasm_i_dsll(buf, rs, rs, 16);
|
|
} else
|
|
uasm_i_dsll32(buf, rs, rs, 0);
|
|
} else
|
|
uasm_i_lui(buf, rs, uasm_rel_hi(addr));
|
|
}
|
|
|
|
void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
|
|
{
|
|
UASM_i_LA_mostly(buf, rs, addr);
|
|
if (uasm_rel_lo(addr)) {
|
|
if (!uasm_in_compat_space_p(addr))
|
|
uasm_i_daddiu(buf, rs, rs, uasm_rel_lo(addr));
|
|
else
|
|
uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
|
|
}
|
|
}
|
|
|
|
/* Handle relocations. */
|
|
void __cpuinit
|
|
uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
|
|
{
|
|
(*rel)->addr = addr;
|
|
(*rel)->type = R_MIPS_PC16;
|
|
(*rel)->lab = lid;
|
|
(*rel)++;
|
|
}
|
|
|
|
static inline void __cpuinit
|
|
__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
|
|
{
|
|
long laddr = (long)lab->addr;
|
|
long raddr = (long)rel->addr;
|
|
|
|
switch (rel->type) {
|
|
case R_MIPS_PC16:
|
|
*rel->addr |= build_bimm(laddr - (raddr + 4));
|
|
break;
|
|
|
|
default:
|
|
panic("Unsupported Micro-assembler relocation %d",
|
|
rel->type);
|
|
}
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
|
|
{
|
|
struct uasm_label *l;
|
|
|
|
for (; rel->lab != UASM_LABEL_INVALID; rel++)
|
|
for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
|
|
if (rel->lab == l->lab)
|
|
__resolve_relocs(rel, l);
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
|
|
{
|
|
for (; rel->lab != UASM_LABEL_INVALID; rel++)
|
|
if (rel->addr >= first && rel->addr < end)
|
|
rel->addr += off;
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
|
|
{
|
|
for (; lab->lab != UASM_LABEL_INVALID; lab++)
|
|
if (lab->addr >= first && lab->addr < end)
|
|
lab->addr += off;
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
|
|
u32 *end, u32 *target)
|
|
{
|
|
long off = (long)(target - first);
|
|
|
|
memcpy(target, first, (end - first) * sizeof(u32));
|
|
|
|
uasm_move_relocs(rel, first, end, off);
|
|
uasm_move_labels(lab, first, end, off);
|
|
}
|
|
|
|
int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
|
|
{
|
|
for (; rel->lab != UASM_LABEL_INVALID; rel++) {
|
|
if (rel->addr == addr
|
|
&& (rel->type == R_MIPS_PC16
|
|
|| rel->type == R_MIPS_26))
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Convenience functions for labeled branches. */
|
|
void __cpuinit
|
|
uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
|
|
{
|
|
uasm_r_mips_pc16(r, *p, lid);
|
|
uasm_i_bltz(p, reg, 0);
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
|
|
{
|
|
uasm_r_mips_pc16(r, *p, lid);
|
|
uasm_i_b(p, 0);
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
|
|
{
|
|
uasm_r_mips_pc16(r, *p, lid);
|
|
uasm_i_beqz(p, reg, 0);
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
|
|
{
|
|
uasm_r_mips_pc16(r, *p, lid);
|
|
uasm_i_beqzl(p, reg, 0);
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
|
|
unsigned int reg2, int lid)
|
|
{
|
|
uasm_r_mips_pc16(r, *p, lid);
|
|
uasm_i_bne(p, reg1, reg2, 0);
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
|
|
{
|
|
uasm_r_mips_pc16(r, *p, lid);
|
|
uasm_i_bnez(p, reg, 0);
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
|
|
{
|
|
uasm_r_mips_pc16(r, *p, lid);
|
|
uasm_i_bgezl(p, reg, 0);
|
|
}
|
|
|
|
void __cpuinit
|
|
uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
|
|
{
|
|
uasm_r_mips_pc16(r, *p, lid);
|
|
uasm_i_bgez(p, reg, 0);
|
|
}
|