forked from luck/tmp_suning_uos_patched
8eae19ccae
The Asus WL520GC and WL520GU are based on the BCM5354 and clocked at 200MHz, but they do not have a clkfreq nvram variable set to the correct value. This adds a workaround for these devices. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5843/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
84 lines
2.5 KiB
C
84 lines
2.5 KiB
C
/*
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* Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/ssb/ssb.h>
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#include <asm/time.h>
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#include <bcm47xx.h>
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#include <bcm47xx_nvram.h>
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#include <bcm47xx_board.h>
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void __init plat_time_init(void)
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{
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unsigned long hz = 0;
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u16 chip_id = 0;
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char buf[10];
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int len;
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enum bcm47xx_board board = bcm47xx_board_get();
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/*
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* Use deterministic values for initial counter interrupt
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* so that calibrate delay avoids encountering a counter wrap.
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*/
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write_c0_count(0);
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write_c0_compare(0xffff);
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switch (bcm47xx_bus_type) {
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#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
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chip_id = bcm47xx_bus.ssb.chip_id;
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break;
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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case BCM47XX_BUS_TYPE_BCMA:
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hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
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chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
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break;
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#endif
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}
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if (chip_id == 0x5354) {
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len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
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if (len >= 0 && !strncmp(buf, "200", 4))
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hz = 100000000;
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}
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switch (board) {
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case BCM47XX_BOARD_ASUS_WL520GC:
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case BCM47XX_BOARD_ASUS_WL520GU:
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hz = 100000000;
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break;
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default:
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break;
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}
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if (!hz)
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hz = 100000000;
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/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
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mips_hpt_frequency = hz;
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}
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