forked from luck/tmp_suning_uos_patched
66bb0aa077
they had small conflicts (respectively within KVM documentation, and with 3.16-rc changes). Since they were all within the subsystem, I took care of them. Stephen Rothwell reported some snags in PPC builds, but they are all fixed now; the latest linux-next report was clean. New features for ARM include: - KVM VGIC v2 emulation on GICv3 hardware - Big-Endian support for arm/arm64 (guest and host) - Debug Architecture support for arm64 (arm32 is on Christoffer's todo list) And for PPC: - Book3S: Good number of LE host fixes, enable HV on LE - Book3S HV: Add in-guest debug support This release drops support for KVM on the PPC440. As a result, the PPC merge removes more lines than it adds. :) I also included an x86 change, since Davidlohr tied it to an independent bug report and the reporter quickly provided a Tested-by; there was no reason to wait for -rc2. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJT4iIJAAoJEBvWZb6bTYbyZqoP/3Wxy8NWPFJ8HGt81NHlGnDS a9UbL7EibcOEG+aaKqmtBglTD5YDiGBDNCxxiSJaDHt+grLN4fsWIliJob1nJFoO 90f89EWN2XjeCrJXA5nUoeg5tpc5OoYKsiP6pTgzIwkP8vvs/H1+zpcTS/UmYsr/ qipVMMsM+zZeHWZcSbqjW88z7YqIn1sr5282wJ85cbyv4KGizb/G4dyPuDqLb6np hkAD8Ah6VV2suQ2FSy7G2fg20R0vglUi60hkEHLoCBPVqJCl7SmC8MvxNbjBnP8S J36R0R0u1wHYKzAGooLJGVOZ/o/gSiVqKX+++L2EvJBN+kuA6u/7fxLyBT+LwDAE IF/Aln5rpg1fe+eywvhz86WljTVEQ8bO1zVsIQUPY+/ZOPedZHMwyvXft8ogbjSp 2m9OJ/3e8Aggh0OeHpCDoeow+QDUXvX0YdCw+2Yh0p+7VMXqkyp0QEiBu38jrusC rB3VNifJbDSWLKdG9LfCAPHnxZD2XYEwv2WFBo6KQOGMGHfx0GXpCOL/jQihrhA6 HtEG5Bs3lvnHQemdpUZ58xojiABbMaUPdcnPXQQEp23WhZzrfLMLzqVG0VYnhSsC 9pi7MJj8c31rqx5WU2oRM28i/BvNxN0NCtkDpineO5s3f89Ws1xnwxqlm38AKP0J irJQTYFEqec+GM9JK1rG =hyQP -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull second round of KVM changes from Paolo Bonzini: "Here are the PPC and ARM changes for KVM, which I separated because they had small conflicts (respectively within KVM documentation, and with 3.16-rc changes). Since they were all within the subsystem, I took care of them. Stephen Rothwell reported some snags in PPC builds, but they are all fixed now; the latest linux-next report was clean. New features for ARM include: - KVM VGIC v2 emulation on GICv3 hardware - Big-Endian support for arm/arm64 (guest and host) - Debug Architecture support for arm64 (arm32 is on Christoffer's todo list) And for PPC: - Book3S: Good number of LE host fixes, enable HV on LE - Book3S HV: Add in-guest debug support This release drops support for KVM on the PPC440. As a result, the PPC merge removes more lines than it adds. :) I also included an x86 change, since Davidlohr tied it to an independent bug report and the reporter quickly provided a Tested-by; there was no reason to wait for -rc2" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (122 commits) KVM: Move more code under CONFIG_HAVE_KVM_IRQFD KVM: nVMX: fix "acknowledge interrupt on exit" when APICv is in use KVM: nVMX: Fix nested vmexit ack intr before load vmcs01 KVM: PPC: Enable IRQFD support for the XICS interrupt controller KVM: Give IRQFD its own separate enabling Kconfig option KVM: Move irq notifier implementation into eventfd.c KVM: Move all accesses to kvm::irq_routing into irqchip.c KVM: irqchip: Provide and use accessors for irq routing table KVM: Don't keep reference to irq routing table in irqfd struct KVM: PPC: drop duplicate tracepoint arm64: KVM: fix 64bit CP15 VM access for 32bit guests KVM: arm64: GICv3: mandate page-aligned GICV region arm64: KVM: GICv3: move system register access to msr_s/mrs_s KVM: PPC: PR: Handle FSCR feature deselects KVM: PPC: HV: Remove generic instruction emulation KVM: PPC: BOOKEHV: rename e500hv_spr to bookehv_spr KVM: PPC: Remove DCR handling KVM: PPC: Expose helper functions for data/inst faults KVM: PPC: Separate loadstore emulation from priv emulation KVM: PPC: Handle magic page in kvmppc_ld/st ...
223 lines
6.2 KiB
ArmAsm
223 lines
6.2 KiB
ArmAsm
/*
|
|
* Copyright (c) 2012 Linaro Limited.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along
|
|
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
|
*/
|
|
|
|
#include <linux/init.h>
|
|
#include <linux/linkage.h>
|
|
#include <asm/assembler.h>
|
|
#include <asm/virt.h>
|
|
|
|
#ifndef ZIMAGE
|
|
/*
|
|
* For the kernel proper, we need to find out the CPU boot mode long after
|
|
* boot, so we need to store it in a writable variable.
|
|
*
|
|
* This is not in .bss, because we set it sufficiently early that the boot-time
|
|
* zeroing of .bss would clobber it.
|
|
*/
|
|
.data
|
|
ENTRY(__boot_cpu_mode)
|
|
.long 0
|
|
.text
|
|
|
|
/*
|
|
* Save the primary CPU boot mode. Requires 3 scratch registers.
|
|
*/
|
|
.macro store_primary_cpu_mode reg1, reg2, reg3
|
|
mrs \reg1, cpsr
|
|
and \reg1, \reg1, #MODE_MASK
|
|
adr \reg2, .L__boot_cpu_mode_offset
|
|
ldr \reg3, [\reg2]
|
|
str \reg1, [\reg2, \reg3]
|
|
.endm
|
|
|
|
/*
|
|
* Compare the current mode with the one saved on the primary CPU.
|
|
* If they don't match, record that fact. The Z bit indicates
|
|
* if there's a match or not.
|
|
* Requires 3 additionnal scratch registers.
|
|
*/
|
|
.macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
|
|
adr \reg2, .L__boot_cpu_mode_offset
|
|
ldr \reg3, [\reg2]
|
|
ldr \reg1, [\reg2, \reg3]
|
|
cmp \mode, \reg1 @ matches primary CPU boot mode?
|
|
orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
|
|
strne \reg1, [\reg2, \reg3] @ record what happened and give up
|
|
.endm
|
|
|
|
#else /* ZIMAGE */
|
|
|
|
.macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req
|
|
.endm
|
|
|
|
/*
|
|
* The zImage loader only runs on one CPU, so we don't bother with mult-CPU
|
|
* consistency checking:
|
|
*/
|
|
.macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
|
|
cmp \mode, \mode
|
|
.endm
|
|
|
|
#endif /* ZIMAGE */
|
|
|
|
/*
|
|
* Hypervisor stub installation functions.
|
|
*
|
|
* These must be called with the MMU and D-cache off.
|
|
* They are not ABI compliant and are only intended to be called from the kernel
|
|
* entry points in head.S.
|
|
*/
|
|
@ Call this from the primary CPU
|
|
ENTRY(__hyp_stub_install)
|
|
store_primary_cpu_mode r4, r5, r6
|
|
ENDPROC(__hyp_stub_install)
|
|
|
|
@ fall through...
|
|
|
|
@ Secondary CPUs should call here
|
|
ENTRY(__hyp_stub_install_secondary)
|
|
mrs r4, cpsr
|
|
and r4, r4, #MODE_MASK
|
|
|
|
/*
|
|
* If the secondary has booted with a different mode, give up
|
|
* immediately.
|
|
*/
|
|
compare_cpu_mode_with_primary r4, r5, r6, r7
|
|
retne lr
|
|
|
|
/*
|
|
* Once we have given up on one CPU, we do not try to install the
|
|
* stub hypervisor on the remaining ones: because the saved boot mode
|
|
* is modified, it can't compare equal to the CPSR mode field any
|
|
* more.
|
|
*
|
|
* Otherwise...
|
|
*/
|
|
|
|
cmp r4, #HYP_MODE
|
|
retne lr @ give up if the CPU is not in HYP mode
|
|
|
|
/*
|
|
* Configure HSCTLR to set correct exception endianness/instruction set
|
|
* state etc.
|
|
* Turn off all traps
|
|
* Eventually, CPU-specific code might be needed -- assume not for now
|
|
*
|
|
* This code relies on the "eret" instruction to synchronize the
|
|
* various coprocessor accesses. This is done when we switch to SVC
|
|
* (see safe_svcmode_maskall).
|
|
*/
|
|
@ Now install the hypervisor stub:
|
|
adr r7, __hyp_stub_vectors
|
|
mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
|
|
|
|
@ Disable all traps, so we don't get any nasty surprise
|
|
mov r7, #0
|
|
mcr p15, 4, r7, c1, c1, 0 @ HCR
|
|
mcr p15, 4, r7, c1, c1, 2 @ HCPTR
|
|
mcr p15, 4, r7, c1, c1, 3 @ HSTR
|
|
|
|
THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
|
|
ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
|
|
mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
|
|
|
|
mrc p15, 4, r7, c1, c1, 1 @ HDCR
|
|
and r7, #0x1f @ Preserve HPMN
|
|
mcr p15, 4, r7, c1, c1, 1 @ HDCR
|
|
|
|
#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
|
|
@ make CNTP_* and CNTPCT accessible from PL1
|
|
mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
|
|
lsr r7, #16
|
|
and r7, #0xf
|
|
cmp r7, #1
|
|
bne 1f
|
|
mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL
|
|
orr r7, r7, #3 @ PL1PCEN | PL1PCTEN
|
|
mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL
|
|
mov r7, #0
|
|
mcrr p15, 4, r7, r7, c14 @ CNTVOFF
|
|
|
|
@ Disable virtual timer in case it was counting
|
|
mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL
|
|
bic r7, #1 @ Clear ENABLE
|
|
mcr p15, 0, r7, c14, c3, 1 @ CNTV_CTL
|
|
1:
|
|
#endif
|
|
|
|
bx lr @ The boot CPU mode is left in r4.
|
|
ENDPROC(__hyp_stub_install_secondary)
|
|
|
|
__hyp_stub_do_trap:
|
|
cmp r0, #-1
|
|
mrceq p15, 4, r0, c12, c0, 0 @ get HVBAR
|
|
mcrne p15, 4, r0, c12, c0, 0 @ set HVBAR
|
|
__ERET
|
|
ENDPROC(__hyp_stub_do_trap)
|
|
|
|
/*
|
|
* __hyp_set_vectors: Call this after boot to set the initial hypervisor
|
|
* vectors as part of hypervisor installation. On an SMP system, this should
|
|
* be called on each CPU.
|
|
*
|
|
* r0 must be the physical address of the new vector table (which must lie in
|
|
* the bottom 4GB of physical address space.
|
|
*
|
|
* r0 must be 32-byte aligned.
|
|
*
|
|
* Before calling this, you must check that the stub hypervisor is installed
|
|
* everywhere, by waiting for any secondary CPUs to be brought up and then
|
|
* checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
|
|
*
|
|
* If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
|
|
* something else went wrong... in such cases, trying to install a new
|
|
* hypervisor is unlikely to work as desired.
|
|
*
|
|
* When you call into your shiny new hypervisor, sp_hyp will contain junk,
|
|
* so you will need to set that to something sensible at the new hypervisor's
|
|
* initialisation entry point.
|
|
*/
|
|
ENTRY(__hyp_get_vectors)
|
|
mov r0, #-1
|
|
ENDPROC(__hyp_get_vectors)
|
|
@ fall through
|
|
ENTRY(__hyp_set_vectors)
|
|
__HVC(0)
|
|
ret lr
|
|
ENDPROC(__hyp_set_vectors)
|
|
|
|
#ifndef ZIMAGE
|
|
.align 2
|
|
.L__boot_cpu_mode_offset:
|
|
.long __boot_cpu_mode - .
|
|
#endif
|
|
|
|
.align 5
|
|
__hyp_stub_vectors:
|
|
__hyp_stub_reset: W(b) .
|
|
__hyp_stub_und: W(b) .
|
|
__hyp_stub_svc: W(b) .
|
|
__hyp_stub_pabort: W(b) .
|
|
__hyp_stub_dabort: W(b) .
|
|
__hyp_stub_trap: W(b) __hyp_stub_do_trap
|
|
__hyp_stub_irq: W(b) .
|
|
__hyp_stub_fiq: W(b) .
|
|
ENDPROC(__hyp_stub_vectors)
|
|
|