forked from luck/tmp_suning_uos_patched
7795566495
The DMA base registers are available in a global named "base_addr" for every Blackfin variant. Give this a more descriptive name, and remove duplicate tables from some drivers. Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by: Bryan Wu <cooloney@kernel.org>
77 lines
1.9 KiB
C
77 lines
1.9 KiB
C
/*
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* file: include/asm-blackfin/mach-bf548/dma.h
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* based on:
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* author:
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*
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* created:
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* description:
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* system mmr register map
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* rev:
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*
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* modified:
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*
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*
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* bugs: enter bugs at http://blackfin.uclinux.org/
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license as published by
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* the free software foundation; either version 2, or (at your option)
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* any later version.
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*
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* this program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* merchantability or fitness for a particular purpose. see the
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* gnu general public license for more details.
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*
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* you should have received a copy of the gnu general public license
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* along with this program; see the file copying.
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* if not, write to the free software foundation,
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* 59 temple place - suite 330, boston, ma 02111-1307, usa.
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*/
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define CH_SPORT0_RX 0
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#define CH_SPORT0_TX 1
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#define CH_SPORT1_RX 2
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#define CH_SPORT1_TX 3
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#define CH_SPI0 4
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#define CH_SPI1 5
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#define CH_UART0_RX 6
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#define CH_UART0_TX 7
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#define CH_UART1_RX 8
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#define CH_UART1_TX 9
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#define CH_ATAPI_RX 10
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#define CH_ATAPI_TX 11
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#define CH_EPPI0 12
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#define CH_EPPI1 13
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#define CH_EPPI2 14
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#define CH_PIXC_IMAGE 15
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#define CH_PIXC_OVERLAY 16
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#define CH_PIXC_OUTPUT 17
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#define CH_SPORT2_RX 18
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#define CH_UART2_RX 18
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#define CH_SPORT2_TX 19
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#define CH_UART2_TX 19
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#define CH_SPORT3_RX 20
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#define CH_UART3_RX 20
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#define CH_SPORT3_TX 21
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#define CH_UART3_TX 21
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#define CH_SDH 22
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#define CH_NFC 22
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#define CH_SPI2 23
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#define CH_MEM_STREAM0_DEST 24
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#define CH_MEM_STREAM0_SRC 25
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#define CH_MEM_STREAM1_DEST 26
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#define CH_MEM_STREAM1_SRC 27
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#define CH_MEM_STREAM2_DEST 28
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#define CH_MEM_STREAM2_SRC 29
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#define CH_MEM_STREAM3_DEST 30
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#define CH_MEM_STREAM3_SRC 31
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#define MAX_BLACKFIN_DMA_CHANNEL 32
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#endif
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