forked from luck/tmp_suning_uos_patched
e24779649c
This patch adds power domain indices for the RZ/G2H (r8a774e1) SoC. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594138692-16816-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
37 lines
1.0 KiB
C
37 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A774E1_PD_CA57_CPU0 0
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#define R8A774E1_PD_CA57_CPU1 1
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#define R8A774E1_PD_CA57_CPU2 2
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#define R8A774E1_PD_CA57_CPU3 3
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#define R8A774E1_PD_CA53_CPU0 5
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#define R8A774E1_PD_CA53_CPU1 6
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#define R8A774E1_PD_CA53_CPU2 7
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#define R8A774E1_PD_CA53_CPU3 8
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#define R8A774E1_PD_A3VP 9
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#define R8A774E1_PD_CA57_SCU 12
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#define R8A774E1_PD_A3VC 14
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#define R8A774E1_PD_3DG_A 17
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#define R8A774E1_PD_3DG_B 18
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#define R8A774E1_PD_3DG_C 19
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#define R8A774E1_PD_3DG_D 20
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#define R8A774E1_PD_CA53_SCU 21
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#define R8A774E1_PD_3DG_E 22
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#define R8A774E1_PD_A2VC1 26
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/* Always-on power area */
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#define R8A774E1_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */
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