forked from luck/tmp_suning_uos_patched
841e37a5ca
Add power domain indices for RZ/G1N (R8A7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
25 lines
678 B
C
25 lines
678 B
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A7744_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A7744_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*
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* Note that RZ/G1N is identical to RZ/G2M w.r.t. power domains.
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*/
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#define R8A7744_PD_CA15_CPU0 0
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#define R8A7744_PD_CA15_CPU1 1
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#define R8A7744_PD_CA15_SCU 12
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#define R8A7744_PD_SGX 20
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/* Always-on power area */
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#define R8A7744_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A7744_SYSC_H__ */
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