forked from luck/tmp_suning_uos_patched
3668b45d46
* architecture specific details are handled in asm/arch/time.h * ARCH_IOP13XX now selects PLAT_IOP * as suggested by Lennert use ifdef CONFIG_XSCALE to skip the cp_wait on XSC3 Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
52 lines
1.0 KiB
C
52 lines
1.0 KiB
C
#ifndef _IOP13XX_TIME_H_
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#define _IOP13XX_TIME_H_
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#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
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#define IOP_TMR_EN 0x02
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#define IOP_TMR_RELOAD 0x04
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#define IOP_TMR_PRIVILEGED 0x08
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#define IOP_TMR_RATIO_1_1 0x00
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void iop_init_time(unsigned long tickrate);
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unsigned long iop_gettimeoffset(void);
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static inline void write_tmr0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
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}
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static inline void write_tmr1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
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}
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static inline u32 read_tcr0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
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return val;
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}
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static inline u32 read_tcr1(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
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return val;
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}
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static inline void write_trr0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
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}
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static inline void write_trr1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
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}
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static inline void write_tisr(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
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}
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#endif
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