forked from luck/tmp_suning_uos_patched
88 lines
2.7 KiB
C
88 lines
2.7 KiB
C
/* include/asm-arm/arch-lh7a40x/constants.h
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*
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* Copyright (C) 2004 Coastal Environmental Systems
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* Copyright (C) 2004 Logic Product Development
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_ARCH_CONSTANTS_H
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#define __ASM_ARCH_CONSTANTS_H
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/* Addressing constants */
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/* SoC CPU IO addressing */
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#define IO_PHYS (0x80000000)
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#define IO_VIRT (0xf8000000)
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#define IO_SIZE (0x0000B000)
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#ifdef CONFIG_MACH_KEV7A400
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# define CPLD_PHYS (0x20000000)
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# define CPLD_VIRT (0xf2000000)
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# define CPLD_SIZE PAGE_SIZE
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#endif
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#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
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# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */
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/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */
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# define IOBARRIER_VIRT 0xf0000000
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# define IOBARRIER_SIZE PAGE_SIZE
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# define CF_PHYS 0x60200000
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# define CF_VIRT 0xf6020000
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# define CF_SIZE (8*1024)
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/* The IO mappings for the LPD CPLD are, unfortunately, sparse. */
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# define CPLDX_PHYS(x) (0x70000000 | ((x) << 20))
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# define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16))
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# define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */
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# define CPLD00_VIRT CPLDX_VIRT (0x00)
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# define CPLD00_SIZE PAGE_SIZE
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# define CPLD02_PHYS CPLDX_PHYS (0x02)
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# define CPLD02_VIRT CPLDX_VIRT (0x02)
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# define CPLD02_SIZE PAGE_SIZE
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# define CPLD06_PHYS CPLDX_PHYS (0x06)
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# define CPLD06_VIRT CPLDX_VIRT (0x06)
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# define CPLD06_SIZE PAGE_SIZE
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# define CPLD08_PHYS CPLDX_PHYS (0x08)
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# define CPLD08_VIRT CPLDX_VIRT (0x08)
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# define CPLD08_SIZE PAGE_SIZE
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# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
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# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
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# define CPLD0C_SIZE PAGE_SIZE
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# define CPLD0E_PHYS CPLDX_PHYS (0x0e)
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# define CPLD0E_VIRT CPLDX_VIRT (0x0e)
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# define CPLD0E_SIZE PAGE_SIZE
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# define CPLD10_PHYS CPLDX_PHYS (0x10)
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# define CPLD10_VIRT CPLDX_VIRT (0x10)
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# define CPLD10_SIZE PAGE_SIZE
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# define CPLD12_PHYS CPLDX_PHYS (0x12)
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# define CPLD12_VIRT CPLDX_VIRT (0x12)
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# define CPLD12_SIZE PAGE_SIZE
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# define CPLD14_PHYS CPLDX_PHYS (0x14)
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# define CPLD14_VIRT CPLDX_VIRT (0x14)
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# define CPLD14_SIZE PAGE_SIZE
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# define CPLD16_PHYS CPLDX_PHYS (0x16)
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# define CPLD16_VIRT CPLDX_VIRT (0x16)
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# define CPLD16_SIZE PAGE_SIZE
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# define CPLD18_PHYS CPLDX_PHYS (0x18)
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# define CPLD18_VIRT CPLDX_VIRT (0x18)
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# define CPLD18_SIZE PAGE_SIZE
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# define CPLD1A_PHYS CPLDX_PHYS (0x1a)
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# define CPLD1A_VIRT CPLDX_VIRT (0x1a)
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# define CPLD1A_SIZE PAGE_SIZE
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#endif
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/* Timing constants */
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#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
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#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
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#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
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#endif /* __ASM_ARCH_CONSTANTS_H */
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