forked from luck/tmp_suning_uos_patched
25097bf153
Currently the storage of the machine flags is a globally exported unsigned long long variable. By moving the storage location into the lowcore struct we allow assembler code to check machine_flags directly even without needing a register. Addtionally the lowcore and therefore the machine flags too will be in cache most of the time. Signed-off-by: Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
502 lines
12 KiB
C
502 lines
12 KiB
C
/*
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* include/asm-s390/ptrace.h
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*
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* S390 version
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* Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
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* Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
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*/
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#ifndef _S390_PTRACE_H
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#define _S390_PTRACE_H
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/*
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* Offsets in the user_regs_struct. They are used for the ptrace
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* system call and in entry.S
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*/
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#ifndef __s390x__
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#define PT_PSWMASK 0x00
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#define PT_PSWADDR 0x04
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#define PT_GPR0 0x08
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#define PT_GPR1 0x0C
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#define PT_GPR2 0x10
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#define PT_GPR3 0x14
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#define PT_GPR4 0x18
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#define PT_GPR5 0x1C
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#define PT_GPR6 0x20
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#define PT_GPR7 0x24
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#define PT_GPR8 0x28
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#define PT_GPR9 0x2C
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#define PT_GPR10 0x30
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#define PT_GPR11 0x34
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#define PT_GPR12 0x38
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#define PT_GPR13 0x3C
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#define PT_GPR14 0x40
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#define PT_GPR15 0x44
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#define PT_ACR0 0x48
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#define PT_ACR1 0x4C
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#define PT_ACR2 0x50
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#define PT_ACR3 0x54
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#define PT_ACR4 0x58
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#define PT_ACR5 0x5C
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#define PT_ACR6 0x60
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#define PT_ACR7 0x64
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#define PT_ACR8 0x68
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#define PT_ACR9 0x6C
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#define PT_ACR10 0x70
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#define PT_ACR11 0x74
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#define PT_ACR12 0x78
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#define PT_ACR13 0x7C
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#define PT_ACR14 0x80
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#define PT_ACR15 0x84
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#define PT_ORIGGPR2 0x88
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#define PT_FPC 0x90
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/*
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* A nasty fact of life that the ptrace api
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* only supports passing of longs.
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*/
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#define PT_FPR0_HI 0x98
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#define PT_FPR0_LO 0x9C
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#define PT_FPR1_HI 0xA0
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#define PT_FPR1_LO 0xA4
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#define PT_FPR2_HI 0xA8
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#define PT_FPR2_LO 0xAC
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#define PT_FPR3_HI 0xB0
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#define PT_FPR3_LO 0xB4
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#define PT_FPR4_HI 0xB8
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#define PT_FPR4_LO 0xBC
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#define PT_FPR5_HI 0xC0
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#define PT_FPR5_LO 0xC4
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#define PT_FPR6_HI 0xC8
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#define PT_FPR6_LO 0xCC
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#define PT_FPR7_HI 0xD0
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#define PT_FPR7_LO 0xD4
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#define PT_FPR8_HI 0xD8
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#define PT_FPR8_LO 0XDC
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#define PT_FPR9_HI 0xE0
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#define PT_FPR9_LO 0xE4
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#define PT_FPR10_HI 0xE8
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#define PT_FPR10_LO 0xEC
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#define PT_FPR11_HI 0xF0
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#define PT_FPR11_LO 0xF4
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#define PT_FPR12_HI 0xF8
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#define PT_FPR12_LO 0xFC
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#define PT_FPR13_HI 0x100
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#define PT_FPR13_LO 0x104
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#define PT_FPR14_HI 0x108
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#define PT_FPR14_LO 0x10C
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#define PT_FPR15_HI 0x110
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#define PT_FPR15_LO 0x114
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#define PT_CR_9 0x118
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#define PT_CR_10 0x11C
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#define PT_CR_11 0x120
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#define PT_IEEE_IP 0x13C
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#define PT_LASTOFF PT_IEEE_IP
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#define PT_ENDREGS 0x140-1
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#define GPR_SIZE 4
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#define CR_SIZE 4
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#define STACK_FRAME_OVERHEAD 96 /* size of minimum stack frame */
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#else /* __s390x__ */
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#define PT_PSWMASK 0x00
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#define PT_PSWADDR 0x08
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#define PT_GPR0 0x10
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#define PT_GPR1 0x18
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#define PT_GPR2 0x20
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#define PT_GPR3 0x28
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#define PT_GPR4 0x30
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#define PT_GPR5 0x38
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#define PT_GPR6 0x40
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#define PT_GPR7 0x48
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#define PT_GPR8 0x50
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#define PT_GPR9 0x58
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#define PT_GPR10 0x60
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#define PT_GPR11 0x68
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#define PT_GPR12 0x70
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#define PT_GPR13 0x78
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#define PT_GPR14 0x80
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#define PT_GPR15 0x88
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#define PT_ACR0 0x90
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#define PT_ACR1 0x94
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#define PT_ACR2 0x98
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#define PT_ACR3 0x9C
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#define PT_ACR4 0xA0
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#define PT_ACR5 0xA4
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#define PT_ACR6 0xA8
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#define PT_ACR7 0xAC
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#define PT_ACR8 0xB0
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#define PT_ACR9 0xB4
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#define PT_ACR10 0xB8
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#define PT_ACR11 0xBC
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#define PT_ACR12 0xC0
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#define PT_ACR13 0xC4
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#define PT_ACR14 0xC8
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#define PT_ACR15 0xCC
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#define PT_ORIGGPR2 0xD0
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#define PT_FPC 0xD8
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#define PT_FPR0 0xE0
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#define PT_FPR1 0xE8
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#define PT_FPR2 0xF0
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#define PT_FPR3 0xF8
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#define PT_FPR4 0x100
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#define PT_FPR5 0x108
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#define PT_FPR6 0x110
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#define PT_FPR7 0x118
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#define PT_FPR8 0x120
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#define PT_FPR9 0x128
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#define PT_FPR10 0x130
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#define PT_FPR11 0x138
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#define PT_FPR12 0x140
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#define PT_FPR13 0x148
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#define PT_FPR14 0x150
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#define PT_FPR15 0x158
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#define PT_CR_9 0x160
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#define PT_CR_10 0x168
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#define PT_CR_11 0x170
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#define PT_IEEE_IP 0x1A8
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#define PT_LASTOFF PT_IEEE_IP
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#define PT_ENDREGS 0x1B0-1
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#define GPR_SIZE 8
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#define CR_SIZE 8
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#define STACK_FRAME_OVERHEAD 160 /* size of minimum stack frame */
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#endif /* __s390x__ */
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#define NUM_GPRS 16
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#define NUM_FPRS 16
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#define NUM_CRS 16
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#define NUM_ACRS 16
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#define NUM_CR_WORDS 3
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#define FPR_SIZE 8
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#define FPC_SIZE 4
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#define FPC_PAD_SIZE 4 /* gcc insists on aligning the fpregs */
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#define ACR_SIZE 4
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#define PTRACE_OLDSETOPTIONS 21
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#ifndef __ASSEMBLY__
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#include <linux/stddef.h>
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#include <linux/types.h>
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typedef union
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{
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float f;
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double d;
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__u64 ui;
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struct
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{
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__u32 hi;
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__u32 lo;
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} fp;
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} freg_t;
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typedef struct
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{
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__u32 fpc;
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freg_t fprs[NUM_FPRS];
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} s390_fp_regs;
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#define FPC_EXCEPTION_MASK 0xF8000000
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#define FPC_FLAGS_MASK 0x00F80000
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#define FPC_DXC_MASK 0x0000FF00
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#define FPC_RM_MASK 0x00000003
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#define FPC_VALID_MASK 0xF8F8FF03
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/* this typedef defines how a Program Status Word looks like */
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typedef struct
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{
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unsigned long mask;
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unsigned long addr;
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} __attribute__ ((aligned(8))) psw_t;
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typedef struct
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{
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__u32 mask;
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__u32 addr;
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} __attribute__ ((aligned(8))) psw_compat_t;
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#ifndef __s390x__
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#define PSW_MASK_PER 0x40000000UL
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#define PSW_MASK_DAT 0x04000000UL
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#define PSW_MASK_IO 0x02000000UL
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#define PSW_MASK_EXT 0x01000000UL
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#define PSW_MASK_KEY 0x00F00000UL
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#define PSW_MASK_MCHECK 0x00040000UL
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#define PSW_MASK_WAIT 0x00020000UL
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#define PSW_MASK_PSTATE 0x00010000UL
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#define PSW_MASK_ASC 0x0000C000UL
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#define PSW_MASK_CC 0x00003000UL
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#define PSW_MASK_PM 0x00000F00UL
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#define PSW_ADDR_AMODE 0x80000000UL
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#define PSW_ADDR_INSN 0x7FFFFFFFUL
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#define PSW_BASE_BITS 0x00080000UL
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#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 20)
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#define PSW_ASC_PRIMARY 0x00000000UL
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#define PSW_ASC_ACCREG 0x00004000UL
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#define PSW_ASC_SECONDARY 0x00008000UL
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#define PSW_ASC_HOME 0x0000C000UL
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#else /* __s390x__ */
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#define PSW_MASK_PER 0x4000000000000000UL
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#define PSW_MASK_DAT 0x0400000000000000UL
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#define PSW_MASK_IO 0x0200000000000000UL
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#define PSW_MASK_EXT 0x0100000000000000UL
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#define PSW_MASK_KEY 0x00F0000000000000UL
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#define PSW_MASK_MCHECK 0x0004000000000000UL
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#define PSW_MASK_WAIT 0x0002000000000000UL
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#define PSW_MASK_PSTATE 0x0001000000000000UL
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#define PSW_MASK_ASC 0x0000C00000000000UL
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#define PSW_MASK_CC 0x0000300000000000UL
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#define PSW_MASK_PM 0x00000F0000000000UL
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#define PSW_ADDR_AMODE 0x0000000000000000UL
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#define PSW_ADDR_INSN 0xFFFFFFFFFFFFFFFFUL
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#define PSW_BASE_BITS 0x0000000180000000UL
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#define PSW_BASE32_BITS 0x0000000080000000UL
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#define PSW_DEFAULT_KEY (((unsigned long) PAGE_DEFAULT_ACC) << 52)
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#define PSW_ASC_PRIMARY 0x0000000000000000UL
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#define PSW_ASC_ACCREG 0x0000400000000000UL
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#define PSW_ASC_SECONDARY 0x0000800000000000UL
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#define PSW_ASC_HOME 0x0000C00000000000UL
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#endif /* __s390x__ */
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#ifdef __KERNEL__
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extern long psw_kernel_bits;
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extern long psw_user_bits;
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#ifdef CONFIG_64BIT
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extern long psw_user32_bits;
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#endif
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#endif
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/* This macro merges a NEW PSW mask specified by the user into
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the currently active PSW mask CURRENT, modifying only those
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bits in CURRENT that the user may be allowed to change: this
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is the condition code and the program mask bits. */
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#define PSW_MASK_MERGE(CURRENT,NEW) \
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(((CURRENT) & ~(PSW_MASK_CC|PSW_MASK_PM)) | \
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((NEW) & (PSW_MASK_CC|PSW_MASK_PM)))
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/*
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* The s390_regs structure is used to define the elf_gregset_t.
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*/
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typedef struct
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{
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psw_t psw;
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unsigned long gprs[NUM_GPRS];
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unsigned int acrs[NUM_ACRS];
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unsigned long orig_gpr2;
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} s390_regs;
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typedef struct
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{
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psw_compat_t psw;
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__u32 gprs[NUM_GPRS];
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__u32 acrs[NUM_ACRS];
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__u32 orig_gpr2;
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} s390_compat_regs;
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#ifdef __KERNEL__
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/*
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* The pt_regs struct defines the way the registers are stored on
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* the stack during a system call.
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*/
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struct pt_regs
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{
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unsigned long args[1];
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psw_t psw;
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unsigned long gprs[NUM_GPRS];
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unsigned long orig_gpr2;
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unsigned short svcnr;
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unsigned short ilc;
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};
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#endif
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/*
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* Now for the program event recording (trace) definitions.
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*/
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typedef struct
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{
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unsigned long cr[NUM_CR_WORDS];
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} per_cr_words;
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#define PER_EM_MASK 0xE8000000UL
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typedef struct
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{
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#ifdef __s390x__
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unsigned : 32;
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#endif /* __s390x__ */
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unsigned em_branching : 1;
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unsigned em_instruction_fetch : 1;
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/*
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* Switching on storage alteration automatically fixes
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* the storage alteration event bit in the users std.
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*/
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unsigned em_storage_alteration : 1;
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unsigned em_gpr_alt_unused : 1;
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unsigned em_store_real_address : 1;
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unsigned : 3;
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unsigned branch_addr_ctl : 1;
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unsigned : 1;
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unsigned storage_alt_space_ctl : 1;
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unsigned : 21;
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unsigned long starting_addr;
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unsigned long ending_addr;
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} per_cr_bits;
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typedef struct
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{
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unsigned short perc_atmid;
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unsigned long address;
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unsigned char access_id;
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} per_lowcore_words;
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typedef struct
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{
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unsigned perc_branching : 1;
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unsigned perc_instruction_fetch : 1;
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unsigned perc_storage_alteration : 1;
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unsigned perc_gpr_alt_unused : 1;
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unsigned perc_store_real_address : 1;
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unsigned : 3;
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unsigned atmid_psw_bit_31 : 1;
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unsigned atmid_validity_bit : 1;
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unsigned atmid_psw_bit_32 : 1;
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unsigned atmid_psw_bit_5 : 1;
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unsigned atmid_psw_bit_16 : 1;
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unsigned atmid_psw_bit_17 : 1;
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unsigned si : 2;
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unsigned long address;
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unsigned : 4;
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unsigned access_id : 4;
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} per_lowcore_bits;
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typedef struct
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{
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union {
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per_cr_words words;
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per_cr_bits bits;
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} control_regs;
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/*
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* Use these flags instead of setting em_instruction_fetch
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* directly they are used so that single stepping can be
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* switched on & off while not affecting other tracing
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*/
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unsigned single_step : 1;
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unsigned instruction_fetch : 1;
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unsigned : 30;
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/*
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* These addresses are copied into cr10 & cr11 if single
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* stepping is switched off
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*/
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unsigned long starting_addr;
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unsigned long ending_addr;
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union {
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per_lowcore_words words;
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per_lowcore_bits bits;
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} lowcore;
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} per_struct;
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typedef struct
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{
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unsigned int len;
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unsigned long kernel_addr;
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unsigned long process_addr;
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} ptrace_area;
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/*
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* S/390 specific non posix ptrace requests. I chose unusual values so
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* they are unlikely to clash with future ptrace definitions.
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*/
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#define PTRACE_PEEKUSR_AREA 0x5000
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#define PTRACE_POKEUSR_AREA 0x5001
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#define PTRACE_PEEKTEXT_AREA 0x5002
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#define PTRACE_PEEKDATA_AREA 0x5003
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#define PTRACE_POKETEXT_AREA 0x5004
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#define PTRACE_POKEDATA_AREA 0x5005
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/*
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* PT_PROT definition is loosely based on hppa bsd definition in
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* gdb/hppab-nat.c
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*/
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#define PTRACE_PROT 21
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typedef enum
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{
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ptprot_set_access_watchpoint,
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ptprot_set_write_watchpoint,
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ptprot_disable_watchpoint
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} ptprot_flags;
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typedef struct
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{
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unsigned long lowaddr;
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unsigned long hiaddr;
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ptprot_flags prot;
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} ptprot_area;
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/* Sequence of bytes for breakpoint illegal instruction. */
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#define S390_BREAKPOINT {0x0,0x1}
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#define S390_BREAKPOINT_U16 ((__u16)0x0001)
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#define S390_SYSCALL_OPCODE ((__u16)0x0a00)
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#define S390_SYSCALL_SIZE 2
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/*
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* The user_regs_struct defines the way the user registers are
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* store on the stack for signal handling.
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*/
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struct user_regs_struct
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{
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psw_t psw;
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unsigned long gprs[NUM_GPRS];
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unsigned int acrs[NUM_ACRS];
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unsigned long orig_gpr2;
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s390_fp_regs fp_regs;
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/*
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* These per registers are in here so that gdb can modify them
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* itself as there is no "official" ptrace interface for hardware
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* watchpoints. This is the way intel does it.
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*/
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per_struct per_info;
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unsigned long ieee_instruction_pointer;
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/* Used to give failing instruction back to user for ieee exceptions */
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};
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#ifdef __KERNEL__
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/*
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* These are defined as per linux/ptrace.h, which see.
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*/
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#define arch_has_single_step() (1)
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struct task_struct;
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extern void user_enable_single_step(struct task_struct *);
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extern void user_disable_single_step(struct task_struct *);
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#define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
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#define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
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#define user_stack_pointer(regs)((regs)->gprs[15])
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#define regs_return_value(regs)((regs)->gprs[2])
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#define profile_pc(regs) instruction_pointer(regs)
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extern void show_regs(struct pt_regs * regs);
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif /* _S390_PTRACE_H */
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