forked from luck/tmp_suning_uos_patched
856fe98f16
Fix paren-placement / precedence bug breaking initialization for 1 MHz clock mode. Also fix comment spelling error, and fence-post (off-by-one) error on symbol used in request_region. Addresses http://bugzilla.kernel.org/show_bug.cgi?id=7242 Thanks alexander.krause@erazor-zone.de, dzpost@dedekind.net, for the reports and patch test, and phelps@mantara.com for the independent patch and verification. Signed-off-by: Jim Cromie <jim.cromie@gmail.com> Cc: <alexander.krause@erazor-zone.de> Cc: <dzpost@dedekind.net> Cc: <phelps@mantara.com> Acked-by: John Stultz <johnstul@us.ibm.com> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
52 lines
1.8 KiB
C
52 lines
1.8 KiB
C
/* linux/include/linux/scx200.h
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Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
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Defines for the National Semiconductor SCx200 Processors
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*/
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/* Interesting stuff for the National Semiconductor SCx200 CPU */
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extern unsigned scx200_cb_base;
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#define scx200_cb_present() (scx200_cb_base!=0)
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/* F0 PCI Header/Bridge Configuration Registers */
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#define SCx200_DOCCS_BASE 0x78 /* DOCCS Base Address Register */
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#define SCx200_DOCCS_CTRL 0x7c /* DOCCS Control Register */
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/* GPIO Register Block */
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#define SCx200_GPIO_SIZE 0x2c /* Size of GPIO register block */
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/* General Configuration Block */
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#define SCx200_CB_BASE_FIXED 0x9000 /* Base fixed at 0x9000 according to errata? */
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/* Watchdog Timer */
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#define SCx200_WDT_OFFSET 0x00 /* offset within configuration block */
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#define SCx200_WDT_SIZE 0x05 /* size */
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#define SCx200_WDT_WDTO 0x00 /* Time-Out Register */
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#define SCx200_WDT_WDCNFG 0x02 /* Configuration Register */
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#define SCx200_WDT_WDSTS 0x04 /* Status Register */
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#define SCx200_WDT_WDSTS_WDOVF (1<<0) /* Overflow bit */
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/* High Resolution Timer */
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#define SCx200_TIMER_OFFSET 0x08
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#define SCx200_TIMER_SIZE 0x06
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/* Clock Generators */
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#define SCx200_CLOCKGEN_OFFSET 0x10
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#define SCx200_CLOCKGEN_SIZE 0x10
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/* Pin Multiplexing and Miscellaneous Configuration Registers */
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#define SCx200_MISC_OFFSET 0x30
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#define SCx200_MISC_SIZE 0x10
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#define SCx200_PMR 0x30 /* Pin Multiplexing Register */
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#define SCx200_MCR 0x34 /* Miscellaneous Configuration Register */
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#define SCx200_INTSEL 0x38 /* Interrupt Selection Register */
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#define SCx200_IID 0x3c /* IA On a Chip Identification Number Reg */
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#define SCx200_REV 0x3d /* Revision Register */
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#define SCx200_CBA 0x3e /* Configuration Base Address Register */
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#define SCx200_CBA_SCRATCH 0x64 /* Configuration Base Address Scratchpad */
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