forked from luck/tmp_suning_uos_patched
85d6943af5
This CPU generates synchronous VFP exceptions in a non-standard way - the FPEXC.EX bit set but without the FPSCR.IXE bit being set like in the VFP subarchitecture 1 or just the FPEXC.DEX bit like in VFP subarchitecture 2. The main problem is that the faulty instruction (which needs to be emulated in software) will be restarted several times (normally until a context switch disables the VFP). This patch ensures that the VFP exception is treated as synchronous. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Nicolas Pitre <nico@cam.org>
270 lines
7.0 KiB
ArmAsm
270 lines
7.0 KiB
ArmAsm
/*
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* linux/arch/arm/vfp/vfphw.S
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*
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* Copyright (C) 2004 ARM Limited.
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* Written by Deep Blue Solutions Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This code is called from the kernel's undefined instruction trap.
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* r9 holds the return address for successful handling.
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* lr holds the return address for unrecognised instructions.
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* r10 points at the start of the private FP workspace in the thread structure
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* sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
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*/
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#include <asm/thread_info.h>
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#include <asm/vfpmacros.h>
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#include "../kernel/entry-header.S"
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.macro DBGSTR, str
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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add r0, pc, #4
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bl printk
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b 1f
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.asciz "<7>VFP: \str\n"
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.balign 4
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1: ldmfd sp!, {r0-r3, ip, lr}
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#endif
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.endm
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.macro DBGSTR1, str, arg
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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mov r1, \arg
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add r0, pc, #4
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bl printk
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b 1f
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.asciz "<7>VFP: \str\n"
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.balign 4
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1: ldmfd sp!, {r0-r3, ip, lr}
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#endif
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.endm
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.macro DBGSTR3, str, arg1, arg2, arg3
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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mov r3, \arg3
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mov r2, \arg2
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mov r1, \arg1
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add r0, pc, #4
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bl printk
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b 1f
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.asciz "<7>VFP: \str\n"
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.balign 4
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1: ldmfd sp!, {r0-r3, ip, lr}
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#endif
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.endm
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@ VFP hardware support entry point.
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@
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@ r0 = faulted instruction
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@ r2 = faulted PC+4
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@ r9 = successful return
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@ r10 = vfp_state union
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@ r11 = CPU number
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@ lr = failure return
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ENTRY(vfp_support_entry)
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DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
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VFPFMRX r1, FPEXC @ Is the VFP enabled?
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DBGSTR1 "fpexc %08x", r1
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tst r1, #FPEXC_EN
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bne look_for_VFP_exceptions @ VFP is already enabled
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DBGSTR1 "enable %x", r10
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ldr r3, last_VFP_context_address
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orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set
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ldr r4, [r3, r11, lsl #2] @ last_VFP_context pointer
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bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled
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cmp r4, r10
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beq check_for_exception @ we are returning to the same
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@ process, so the registers are
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@ still there. In this case, we do
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@ not want to drop a pending exception.
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VFPFMXR FPEXC, r5 @ enable VFP, disable any pending
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@ exceptions, so we can get at the
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@ rest of it
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#ifndef CONFIG_SMP
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@ Save out the current registers to the old thread state
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@ No need for SMP since this is not done lazily
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DBGSTR1 "save old state %p", r4
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cmp r4, #0
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beq no_old_VFP_process
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VFPFSTMIA r4, r5 @ save the working registers
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VFPFMRX r5, FPSCR @ current status
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#ifndef CONFIG_CPU_FEROCEON
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tst r1, #FPEXC_EX @ is there additional state to save?
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beq 1f
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VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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beq 1f
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VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present)
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1:
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#endif
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stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
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@ and point r4 at the word at the
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@ start of the register dump
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#endif
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no_old_VFP_process:
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DBGSTR1 "load state %p", r10
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str r10, [r3, r11, lsl #2] @ update the last_VFP_context pointer
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@ Load the saved state back into the VFP
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VFPFLDMIA r10, r5 @ reload the working registers while
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@ FPEXC is in a safe state
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ldmia r10, {r1, r5, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
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#ifndef CONFIG_CPU_FEROCEON
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tst r1, #FPEXC_EX @ is there additional state to restore?
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beq 1f
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VFPFMXR FPINST, r6 @ restore FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to write?
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beq 1f
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VFPFMXR FPINST2, r8 @ FPINST2 if needed (and present)
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1:
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#endif
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VFPFMXR FPSCR, r5 @ restore status
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check_for_exception:
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tst r1, #FPEXC_EX
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bne process_exception @ might as well handle the pending
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@ exception before retrying branch
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@ out before setting an FPEXC that
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@ stops us reading stuff
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VFPFMXR FPEXC, r1 @ restore FPEXC last
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sub r2, r2, #4
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str r2, [sp, #S_PC] @ retry the instruction
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#ifdef CONFIG_PREEMPT
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get_thread_info r10
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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sub r11, r4, #1 @ decrement it
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str r11, [r10, #TI_PREEMPT]
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#endif
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mov pc, r9 @ we think we have handled things
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look_for_VFP_exceptions:
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@ Check for synchronous or asynchronous exception
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tst r1, #FPEXC_EX | FPEXC_DEX
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bne process_exception
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@ On some implementations of the VFP subarch 1, setting FPSCR.IXE
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@ causes all the CDP instructions to be bounced synchronously without
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@ setting the FPEXC.EX bit
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VFPFMRX r5, FPSCR
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tst r5, #FPSCR_IXE
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bne process_exception
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@ Fall into hand on to next handler - appropriate coproc instr
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@ not recognised by VFP
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DBGSTR "not VFP"
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#ifdef CONFIG_PREEMPT
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get_thread_info r10
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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sub r11, r4, #1 @ decrement it
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str r11, [r10, #TI_PREEMPT]
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#endif
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mov pc, lr
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process_exception:
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DBGSTR "bounce"
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mov r2, sp @ nothing stacked - regdump is at TOS
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mov lr, r9 @ setup for a return to the user code.
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@ Now call the C code to package up the bounce to the support code
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@ r0 holds the trigger instruction
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@ r1 holds the FPEXC value
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@ r2 pointer to register dump
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b VFP_bounce @ we have handled this - the support
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@ code will raise an exception if
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@ required. If not, the user code will
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@ retry the faulted instruction
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ENDPROC(vfp_support_entry)
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ENTRY(vfp_save_state)
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@ Save the current VFP state
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@ r0 - save location
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@ r1 - FPEXC
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DBGSTR1 "save VFP state %p", r0
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VFPFSTMIA r0, r2 @ save the working registers
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VFPFMRX r2, FPSCR @ current status
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tst r1, #FPEXC_EX @ is there additional state to save?
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beq 1f
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VFPFMRX r3, FPINST @ FPINST (only if FPEXC.EX is set)
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tst r1, #FPEXC_FP2V @ is there an FPINST2 to read?
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beq 1f
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VFPFMRX r12, FPINST2 @ FPINST2 if needed (and present)
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1:
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stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2
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mov pc, lr
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ENDPROC(vfp_save_state)
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last_VFP_context_address:
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.word last_VFP_context
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ENTRY(vfp_get_float)
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add pc, pc, r0, lsl #3
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mov r0, r0
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
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mov pc, lr
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mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
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mov pc, lr
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.endr
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ENDPROC(vfp_get_float)
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ENTRY(vfp_put_float)
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add pc, pc, r1, lsl #3
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mov r0, r0
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
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mov pc, lr
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mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
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mov pc, lr
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.endr
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ENDPROC(vfp_put_float)
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ENTRY(vfp_get_double)
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add pc, pc, r0, lsl #3
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mov r0, r0
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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fmrrd r0, r1, d\dr
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mov pc, lr
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.endr
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#ifdef CONFIG_VFPv3
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@ d16 - d31 registers
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
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mov pc, lr
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.endr
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#endif
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@ virtual register 16 (or 32 if VFPv3) for compare with zero
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mov r0, #0
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mov r1, #0
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mov pc, lr
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ENDPROC(vfp_get_double)
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ENTRY(vfp_put_double)
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add pc, pc, r2, lsl #3
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mov r0, r0
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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fmdrr d\dr, r0, r1
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mov pc, lr
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.endr
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#ifdef CONFIG_VFPv3
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@ d16 - d31 registers
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.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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mcrr p11, 3, r1, r2, c\dr @ fmdrr r1, r2, d\dr
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mov pc, lr
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.endr
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#endif
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ENDPROC(vfp_put_double)
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