forked from luck/tmp_suning_uos_patched
07613ba2f4
This switches AGP to use an array of pages for tracking the pages allocated to the GART. This should enable GEM on PAE to work a lot better as we can pass highmem pages to the PAT code and it will do the right thing with them. Signed-off-by: Dave Airlie <airlied@redhat.com>
423 lines
10 KiB
C
423 lines
10 KiB
C
/*
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* ALi AGPGART routines.
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/agp_backend.h>
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#include <asm/page.h> /* PAGE_SIZE */
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#include "agp.h"
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#define ALI_AGPCTRL 0xb8
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#define ALI_ATTBASE 0xbc
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#define ALI_TLBCTRL 0xc0
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#define ALI_TAGCTRL 0xc4
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#define ALI_CACHE_FLUSH_CTRL 0xD0
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#define ALI_CACHE_FLUSH_ADDR_MASK 0xFFFFF000
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#define ALI_CACHE_FLUSH_EN 0x100
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static int ali_fetch_size(void)
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{
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int i;
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u32 temp;
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struct aper_size_info_32 *values;
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pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
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temp &= ~(0xfffffff0);
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values = A_SIZE_32(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static void ali_tlbflush(struct agp_memory *mem)
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{
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u32 temp;
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pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
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temp &= 0xfffffff0;
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temp |= (1<<0 | 1<<1);
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pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL, temp);
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}
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static void ali_cleanup(void)
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{
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struct aper_size_info_32 *previous_size;
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u32 temp;
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previous_size = A_SIZE_32(agp_bridge->previous_size);
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pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
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// clear tag
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pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
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((temp & 0xffffff00) | 0x00000001|0x00000002));
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pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
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pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE,
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((temp & 0x00000ff0) | previous_size->size_value));
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}
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static int ali_configure(void)
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{
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u32 temp;
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struct aper_size_info_32 *current_size;
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current_size = A_SIZE_32(agp_bridge->current_size);
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/* aperture size and gatt addr */
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pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
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temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000))
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| (current_size->size_value & 0xf));
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pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp);
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/* tlb control */
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pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
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pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
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/* address to map to */
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pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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#if 0
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if (agp_bridge->type == ALI_M1541) {
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u32 nlvm_addr = 0;
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switch (current_size->size_value) {
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case 0: break;
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case 1: nlvm_addr = 0x100000;break;
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case 2: nlvm_addr = 0x200000;break;
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case 3: nlvm_addr = 0x400000;break;
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case 4: nlvm_addr = 0x800000;break;
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case 6: nlvm_addr = 0x1000000;break;
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case 7: nlvm_addr = 0x2000000;break;
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case 8: nlvm_addr = 0x4000000;break;
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case 9: nlvm_addr = 0x8000000;break;
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case 10: nlvm_addr = 0x10000000;break;
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default: break;
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}
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nlvm_addr--;
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nlvm_addr&=0xfff00000;
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nlvm_addr+= agp_bridge->gart_bus_addr;
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nlvm_addr|=(agp_bridge->gart_bus_addr>>12);
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dev_info(&agp_bridge->dev->dev, "nlvm top &base = %8x\n",
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nlvm_addr);
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}
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#endif
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pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
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temp &= 0xffffff7f; //enable TLB
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pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp);
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return 0;
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}
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static void m1541_cache_flush(void)
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{
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int i, page_count;
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u32 temp;
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global_cache_flush();
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page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order;
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for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) {
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pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
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&temp);
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pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
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(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
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(agp_bridge->gatt_bus_addr + i)) |
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ALI_CACHE_FLUSH_EN));
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}
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}
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static struct page *m1541_alloc_page(struct agp_bridge_data *bridge)
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{
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struct page *page = agp_generic_alloc_page(agp_bridge);
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u32 temp;
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if (!page)
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return NULL;
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pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
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pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
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(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
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phys_to_gart(page_to_phys(page))) | ALI_CACHE_FLUSH_EN ));
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return page;
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}
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static void ali_destroy_page(struct page *page, int flags)
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{
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if (page) {
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if (flags & AGP_PAGE_DESTROY_UNMAP) {
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global_cache_flush(); /* is this really needed? --hch */
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agp_generic_destroy_page(page, flags);
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} else
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agp_generic_destroy_page(page, flags);
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}
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}
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static void m1541_destroy_page(struct page *page, int flags)
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{
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u32 temp;
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if (page == NULL)
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return;
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if (flags & AGP_PAGE_DESTROY_UNMAP) {
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global_cache_flush();
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pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
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pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
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(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
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phys_to_gart(page_to_phys(page))) | ALI_CACHE_FLUSH_EN));
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}
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agp_generic_destroy_page(page, flags);
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}
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/* Setup function */
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static const struct aper_size_info_32 ali_generic_sizes[7] =
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{
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{256, 65536, 6, 10},
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{128, 32768, 5, 9},
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{64, 16384, 4, 8},
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{32, 8192, 3, 7},
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{16, 4096, 2, 6},
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{8, 2048, 1, 4},
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{4, 1024, 0, 3}
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};
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static const struct agp_bridge_driver ali_generic_bridge = {
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.owner = THIS_MODULE,
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.aperture_sizes = ali_generic_sizes,
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.size_type = U32_APER_SIZE,
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.num_aperture_sizes = 7,
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.configure = ali_configure,
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.fetch_size = ali_fetch_size,
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.cleanup = ali_cleanup,
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.tlb_flush = ali_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = NULL,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = agp_generic_create_gatt_table,
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.free_gatt_table = agp_generic_free_gatt_table,
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.insert_memory = agp_generic_insert_memory,
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.remove_memory = agp_generic_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_destroy_page = ali_destroy_page,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static const struct agp_bridge_driver ali_m1541_bridge = {
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.owner = THIS_MODULE,
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.aperture_sizes = ali_generic_sizes,
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.size_type = U32_APER_SIZE,
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.num_aperture_sizes = 7,
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.configure = ali_configure,
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.fetch_size = ali_fetch_size,
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.cleanup = ali_cleanup,
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.tlb_flush = ali_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = NULL,
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.agp_enable = agp_generic_enable,
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.cache_flush = m1541_cache_flush,
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.create_gatt_table = agp_generic_create_gatt_table,
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.free_gatt_table = agp_generic_free_gatt_table,
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.insert_memory = agp_generic_insert_memory,
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.remove_memory = agp_generic_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = m1541_alloc_page,
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.agp_destroy_page = m1541_destroy_page,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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static struct agp_device_ids ali_agp_device_ids[] __devinitdata =
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{
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{
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.device_id = PCI_DEVICE_ID_AL_M1541,
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.chipset_name = "M1541",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1621,
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.chipset_name = "M1621",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1631,
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.chipset_name = "M1631",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1632,
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.chipset_name = "M1632",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1641,
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.chipset_name = "M1641",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1644,
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.chipset_name = "M1644",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1647,
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.chipset_name = "M1647",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1651,
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.chipset_name = "M1651",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1671,
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.chipset_name = "M1671",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1681,
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.chipset_name = "M1681",
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},
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{
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.device_id = PCI_DEVICE_ID_AL_M1683,
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.chipset_name = "M1683",
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},
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{ }, /* dummy final entry, always present */
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};
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static int __devinit agp_ali_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct agp_device_ids *devs = ali_agp_device_ids;
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struct agp_bridge_data *bridge;
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u8 hidden_1621_id, cap_ptr;
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int j;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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if (!cap_ptr)
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return -ENODEV;
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/* probe for known chipsets */
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for (j = 0; devs[j].chipset_name; j++) {
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if (pdev->device == devs[j].device_id)
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goto found;
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}
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dev_err(&pdev->dev, "unsupported ALi chipset [%04x/%04x])\n",
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pdev->vendor, pdev->device);
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return -ENODEV;
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found:
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bridge = agp_alloc_bridge();
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if (!bridge)
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return -ENOMEM;
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bridge->dev = pdev;
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bridge->capndx = cap_ptr;
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switch (pdev->device) {
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case PCI_DEVICE_ID_AL_M1541:
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bridge->driver = &ali_m1541_bridge;
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break;
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case PCI_DEVICE_ID_AL_M1621:
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pci_read_config_byte(pdev, 0xFB, &hidden_1621_id);
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switch (hidden_1621_id) {
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case 0x31:
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devs[j].chipset_name = "M1631";
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break;
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case 0x32:
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devs[j].chipset_name = "M1632";
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break;
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case 0x41:
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devs[j].chipset_name = "M1641";
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break;
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case 0x43:
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devs[j].chipset_name = "M1621";
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break;
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case 0x47:
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devs[j].chipset_name = "M1647";
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break;
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case 0x51:
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devs[j].chipset_name = "M1651";
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break;
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default:
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break;
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}
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/*FALLTHROUGH*/
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default:
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bridge->driver = &ali_generic_bridge;
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}
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dev_info(&pdev->dev, "ALi %s chipset\n", devs[j].chipset_name);
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/* Fill in the mode register */
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pci_read_config_dword(pdev,
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bridge->capndx+PCI_AGP_STATUS,
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&bridge->mode);
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pci_set_drvdata(pdev, bridge);
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return agp_add_bridge(bridge);
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}
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static void __devexit agp_ali_remove(struct pci_dev *pdev)
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{
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struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
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agp_remove_bridge(bridge);
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agp_put_bridge(bridge);
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}
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static struct pci_device_id agp_ali_pci_table[] = {
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{
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.class = (PCI_CLASS_BRIDGE_HOST << 8),
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.class_mask = ~0,
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.vendor = PCI_VENDOR_ID_AL,
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.device = PCI_ANY_ID,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(pci, agp_ali_pci_table);
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static struct pci_driver agp_ali_pci_driver = {
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.name = "agpgart-ali",
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.id_table = agp_ali_pci_table,
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.probe = agp_ali_probe,
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.remove = agp_ali_remove,
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};
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static int __init agp_ali_init(void)
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{
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if (agp_off)
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return -EINVAL;
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return pci_register_driver(&agp_ali_pci_driver);
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}
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static void __exit agp_ali_cleanup(void)
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{
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pci_unregister_driver(&agp_ali_pci_driver);
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}
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module_init(agp_ali_init);
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module_exit(agp_ali_cleanup);
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MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
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MODULE_LICENSE("GPL and additional rights");
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