forked from luck/tmp_suning_uos_patched
34fa9b2177
The M54[78]x ColdFire parts are not the only members of the ColdFire family that have an MMU. But currently some of the early MMU initialization code is inside the startup code specific to only the ColdFire M54[78]x parts. Move that early ColdFire MMU init code so that it is run for other ColdFire parts running with MMU enabled. Specifically this means that the MMU initialization code will now also be run for the ColdFire M5441x parts when running with MMU enabled. The code move meant that the extern definition for the mmu_context_init() function had to be moved as well. To make it clear that is ColdFire specific I have renamed that with a "cf_" in front of it and put its extern definition in the mcfmmu.h (which is already included by the setup code). Reported-by: Angelo Dureghello <angelo@sysam.it> Tested-by: Angelo Dureghello <angelo@sysam.it> Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/***************************************************************************/
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/*
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* m54xx.c -- platform support for ColdFire 54xx based boards
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*
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* Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/clk.h>
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#include <linux/bootmem.h>
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#include <asm/pgalloc.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/m54xxsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfclk.h>
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#include <asm/m54xxgpt.h>
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#ifdef CONFIG_MMU
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#include <asm/mmu_context.h>
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#endif
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/***************************************************************************/
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DEFINE_CLK(pll, "pll.0", MCF_CLK);
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DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
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DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
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DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
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DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
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DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
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DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
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DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
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DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
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struct clk *mcf_clks[] = {
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&clk_pll,
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&clk_sys,
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&clk_mcfslt0,
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&clk_mcfslt1,
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&clk_mcfuart0,
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&clk_mcfuart1,
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&clk_mcfuart2,
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&clk_mcfuart3,
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&clk_mcfi2c0,
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NULL
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};
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/***************************************************************************/
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static void __init m54xx_uarts_init(void)
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{
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/* enable io pins */
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__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
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__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
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MCFGPIO_PAR_PSC1);
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__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
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MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
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__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
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}
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/***************************************************************************/
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static void __init m54xx_i2c_init(void)
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{
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#if IS_ENABLED(CONFIG_I2C_IMX)
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u32 r;
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/* set the fec/i2c/irq pin assignment register for i2c */
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r = readl(MCF_PAR_FECI2CIRQ);
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r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
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writel(r, MCF_PAR_FECI2CIRQ);
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#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
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}
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/***************************************************************************/
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static void mcf54xx_reset(void)
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{
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/* disable interrupts and enable the watchdog */
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asm("movew #0x2700, %sr\n");
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__raw_writel(0, MCF_GPT_GMS0);
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__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
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__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
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MCF_GPT_GMS0);
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_reset = mcf54xx_reset;
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mach_sched_init = hw_timer_init;
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m54xx_uarts_init();
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m54xx_i2c_init();
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}
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/***************************************************************************/
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