forked from luck/tmp_suning_uos_patched
115 lines
2.9 KiB
ArmAsm
115 lines
2.9 KiB
ArmAsm
/*
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* FILE NAME
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* arch/mips/vr41xx/common/int-handler.S
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*
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* BRIEF MODULE DESCRIPTION
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* Interrupt dispatcher for the NEC VR4100 series.
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*
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* Author: Yoichi Yuasa
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* yyuasa@mvista.com or source@mvista.com
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*
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* Copyright 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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* Changes:
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* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
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* - New creation, NEC VR4100 series are supported.
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*
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* Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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* - Coped with INTASSIGN of NEC VR4133.
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*/
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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.text
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.set noreorder
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.align 5
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NESTED(vr41xx_handle_interrupt, PT_SIZE, ra)
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.set noat
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SAVE_ALL
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CLI
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.set at
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.set noreorder
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/*
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* Get the pending interrupts
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*/
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mfc0 t0, CP0_CAUSE
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mfc0 t1, CP0_STATUS
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andi t0, 0xff00
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and t0, t0, t1
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andi t1, t0, CAUSEF_IP7 # MIPS timer interrupt
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bnez t1, handle_irq
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li a0, 7
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andi t1, t0, 0x7800 # check for Int1-4
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beqz t1, 1f
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andi t1, t0, CAUSEF_IP3 # check for Int1
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bnez t1, handle_int
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li a0, 3
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andi t1, t0, CAUSEF_IP4 # check for Int2
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bnez t1, handle_int
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li a0, 4
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andi t1, t0, CAUSEF_IP5 # check for Int3
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bnez t1, handle_int
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li a0, 5
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andi t1, t0, CAUSEF_IP6 # check for Int4
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bnez t1, handle_int
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li a0, 6
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1:
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andi t1, t0, CAUSEF_IP2 # check for Int0
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bnez t1, handle_int
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li a0, 2
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andi t1, t0, CAUSEF_IP0 # check for IP0
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bnez t1, handle_irq
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li a0, 0
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andi t1, t0, CAUSEF_IP1 # check for IP1
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bnez t1, handle_irq
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li a0, 1
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j spurious_interrupt
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nop
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handle_int:
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jal irq_dispatch
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move a1, sp
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j ret_from_irq
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nop
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handle_irq:
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jal do_IRQ
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move a1, sp
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j ret_from_irq
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END(vr41xx_handle_interrupt)
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