forked from luck/tmp_suning_uos_patched
3957d63da0
While cleaning up the internal API focussing on Fiber and CX4 code we found that I had broken the copper PHY initialization code. This patch restores the PHY-specific code. This is mostly uninteresting since no copper PHY boards are yet available. The changes have been tested against Fiber only as I do not even have copper PHY versions of 82598 macs. This change actually cleans up the API code a bit more and we lose some initialization code. A few PHY link detection helper lines of code have been snuck into this patch, as well as a read flush where it was suspected that this might cause issues. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
50 lines
2.0 KiB
C
50 lines
2.0 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2007 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _IXGBE_PHY_H_
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#define _IXGBE_PHY_H_
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#include "ixgbe_type.h"
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s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
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s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, u32 *speed, bool *link_up);
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s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, u32 speed, bool autoneg,
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bool autoneg_wait_to_complete);
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s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
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s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
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s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 *phy_data);
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/* PHY specific */
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s32 ixgbe_setup_tnx_phy_link(struct ixgbe_hw *hw);
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s32 ixgbe_check_tnx_phy_link(struct ixgbe_hw *hw, u32 *speed, bool *link_up);
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s32 ixgbe_setup_tnx_phy_link_speed(struct ixgbe_hw *hw, u32 speed, bool autoneg,
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bool autoneg_wait_to_complete);
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#endif /* _IXGBE_PHY_H_ */
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