forked from luck/tmp_suning_uos_patched
bea771751c
PCI host bridge setup for SNI RM machines with PCI is quite broken, now that Linux does it's resource setup own its own. It will use IO addresses, which are needed by the EISA config detection and assigns PCI memory addresses, which overlap with ISA legacy addresses (video ram). Below is a patch, which changes the way how the PCI memory addresses are used and sets the minimum IO address to give enough IO space for 8 EISA slots). This patch needs the other PCI resource change, I've posted. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
306 lines
6.6 KiB
C
306 lines
6.6 KiB
C
/*
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* PCIMT specific code
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 97, 98, 2000, 03, 04, 06 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/serial_8250.h>
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#include <asm/mc146818-time.h>
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#include <asm/sni.h>
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#include <asm/time.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#define cacheconf (*(volatile unsigned int *)PCIMT_CACHECONF)
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#define invspace (*(volatile unsigned int *)PCIMT_INVSPACE)
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static void __init sni_pcimt_sc_init(void)
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{
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unsigned int scsiz, sc_size;
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scsiz = cacheconf & 7;
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if (scsiz == 0) {
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printk("Second level cache is deactived.\n");
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return;
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}
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if (scsiz >= 6) {
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printk("Invalid second level cache size configured, "
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"deactivating second level cache.\n");
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cacheconf = 0;
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return;
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}
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sc_size = 128 << scsiz;
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printk("%dkb second level cache detected, deactivating.\n", sc_size);
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cacheconf = 0;
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}
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/*
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* A bit more gossip about the iron we're running on ...
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*/
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static inline void sni_pcimt_detect(void)
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{
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char boardtype[80];
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unsigned char csmsr;
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char *p = boardtype;
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unsigned int asic;
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csmsr = *(volatile unsigned char *)PCIMT_CSMSR;
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p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
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if ((csmsr & 0x80) == 0)
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p += sprintf(p, ", board revision %s",
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(csmsr & 0x20) ? "D" : "C");
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asic = csmsr & 0x80;
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asic = (csmsr & 0x08) ? asic : !asic;
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p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");
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printk("%s.\n", boardtype);
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}
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#define PORT(_base,_irq) \
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{ \
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.iobase = _base, \
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.irq = _irq, \
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.uartclk = 1843200, \
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.iotype = UPIO_PORT, \
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.flags = UPF_BOOT_AUTOCONF, \
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}
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static struct plat_serial8250_port pcimt_data[] = {
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PORT(0x3f8, 4),
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PORT(0x2f8, 3),
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{ },
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};
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static struct platform_device pcimt_serial8250_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = pcimt_data,
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},
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};
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static struct resource sni_io_resource = {
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.start = 0x00000000UL,
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.end = 0x03bfffffUL,
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.name = "PCIMT IO MEM",
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.flags = IORESOURCE_IO,
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};
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static struct resource pcimt_io_resources[] = {
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{
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.start = 0x00,
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.end = 0x1f,
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.name = "dma1",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x40,
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.end = 0x5f,
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.name = "timer",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x60,
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.end = 0x6f,
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.name = "keyboard",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0x80,
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.end = 0x8f,
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.name = "dma page reg",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0xc0,
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.end = 0xdf,
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.name = "dma2",
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.flags = IORESOURCE_BUSY
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}, {
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.start = 0xcfc,
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.end = 0xcff,
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.name = "PCI config data",
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.flags = IORESOURCE_BUSY
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}
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};
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static struct resource sni_mem_resource = {
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.start = 0x18000000UL,
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.end = 0x1fbfffffUL,
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.name = "PCIMT PCI MEM",
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.flags = IORESOURCE_MEM
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};
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static void __init sni_pcimt_resource_init(void)
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{
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int i;
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/* request I/O space for devices used on all i[345]86 PCs */
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for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
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request_resource(&sni_io_resource, pcimt_io_resources + i);
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}
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extern struct pci_ops sni_pcimt_ops;
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static struct pci_controller sni_controller = {
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.pci_ops = &sni_pcimt_ops,
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.mem_resource = &sni_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &sni_io_resource,
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.io_offset = 0x00000000UL,
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.io_map_base = SNI_PORT_BASE
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};
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static void enable_pcimt_irq(unsigned int irq)
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{
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unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
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*(volatile u8 *) PCIMT_IRQSEL |= mask;
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}
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void disable_pcimt_irq(unsigned int irq)
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{
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unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
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*(volatile u8 *) PCIMT_IRQSEL &= mask;
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}
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static void end_pcimt_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_pcimt_irq(irq);
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}
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static struct irq_chip pcimt_irq_type = {
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.typename = "PCIMT",
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.ack = disable_pcimt_irq,
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.mask = disable_pcimt_irq,
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.mask_ack = disable_pcimt_irq,
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.unmask = enable_pcimt_irq,
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.end = end_pcimt_irq,
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};
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/*
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* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
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* button interrupts. Later ...
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*/
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static void pcimt_hwint0(void)
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{
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panic("Received int0 but no handler yet ...");
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}
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/*
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* hwint 1 deals with EISA and SCSI interrupts,
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*
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* The EISA_INT bit in CSITPEND is high active, all others are low active.
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*/
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static void pcimt_hwint1(void)
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{
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u8 pend = *(volatile char *)PCIMT_CSITPEND;
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unsigned long flags;
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if (pend & IT_EISA) {
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int irq;
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/*
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* Note: ASIC PCI's builtin interrupt achknowledge feature is
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* broken. Using it may result in loss of some or all i8259
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* interupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
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*/
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irq = i8259_irq();
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if (unlikely(irq < 0))
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return;
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do_IRQ(irq);
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}
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if (!(pend & IT_SCSI)) {
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flags = read_c0_status();
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clear_c0_status(ST0_IM);
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do_IRQ(PCIMT_IRQ_SCSI);
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write_c0_status(flags);
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}
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}
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/*
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* hwint 3 should deal with the PCI A - D interrupts,
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*/
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static void pcimt_hwint3(void)
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{
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u8 pend = *(volatile char *)PCIMT_CSITPEND;
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int irq;
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pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
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pend ^= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
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clear_c0_status(IE_IRQ3);
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irq = PCIMT_IRQ_INT2 + ffs(pend) - 1;
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do_IRQ(irq);
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set_c0_status(IE_IRQ3);
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}
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static void sni_pcimt_hwint(void)
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{
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u32 pending = read_c0_cause() & read_c0_status();
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if (pending & C_IRQ5)
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do_IRQ (MIPS_CPU_IRQ_BASE + 7);
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else if (pending & C_IRQ4)
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do_IRQ (MIPS_CPU_IRQ_BASE + 6);
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else if (pending & C_IRQ3)
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pcimt_hwint3();
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else if (pending & C_IRQ1)
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pcimt_hwint1();
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else if (pending & C_IRQ0) {
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pcimt_hwint0();
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}
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}
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void __init sni_pcimt_irq_init(void)
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{
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int i;
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*(volatile u8 *) PCIMT_IRQSEL = IT_ETH | IT_EISA;
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mips_cpu_irq_init();
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/* Actually we've got more interrupts to handle ... */
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for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
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set_irq_chip(i, &pcimt_irq_type);
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sni_hwint = sni_pcimt_hwint;
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change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
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}
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void sni_pcimt_init(void)
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{
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sni_pcimt_detect();
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sni_pcimt_sc_init();
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rtc_mips_get_time = mc146818_get_cmos_time;
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rtc_mips_set_time = mc146818_set_rtc_mmss;
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board_time_init = sni_cpu_time_init;
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ioport_resource.end = sni_io_resource.end;
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#ifdef CONFIG_PCI
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PCIBIOS_MIN_IO = 0x9000;
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register_pci_controller(&sni_controller);
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#endif
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sni_pcimt_resource_init();
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}
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static int __init snirm_pcimt_setup_devinit(void)
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{
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switch (sni_brd_type) {
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case SNI_BRD_PCI_MTOWER:
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case SNI_BRD_PCI_DESKTOP:
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case SNI_BRD_PCI_MTOWER_CPLUS:
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platform_device_register(&pcimt_serial8250_device);
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break;
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}
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return 0;
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}
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device_initcall(snirm_pcimt_setup_devinit);
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