forked from luck/tmp_suning_uos_patched
85b6fcadcf
The two drivers used for Ux500 sched_clock use two Kconfig symbols to select which of the two gets used as sched_clock. This isn't right: the workaround is trying to make sure that the NONSTOP timer is used for sched_clock in order to keep that clock ticking consistently over a suspend/resume cycle. (Otherwise sched_clock simply stops during suspend and continues after resume). This will notably affect any timetstamped debug prints, so that they show the absolute number of seconds since the system was booted and does not loose wall-clock time during suspend and resume as if time stood still. The real way to fix this problem is to make sched_clock take advantage of any NONSTOP clock source on the system and adjust accordingly, not to try to work around this by using a different sched_clock depending on what system we are compiling for. This can solve the problem for everyone instead of providing a local solution. Cc: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
73 lines
2.1 KiB
C
73 lines
2.1 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2011
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*
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* License Terms: GNU General Public License v2
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* Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
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* Author: Sundar Iyer for ST-Ericsson
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* sched_clock implementation is based on:
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* plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
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*
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* DBx500-PRCMU Timer
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* The PRCMU has 5 timers which are available in a always-on
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* power domain. We use the Timer 4 for our always-on clock
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* source on DB8500.
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clockchips.h>
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#define RATE_32K 32768
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#define TIMER_MODE_CONTINOUS 0x1
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#define TIMER_DOWNCOUNT_VAL 0xffffffff
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#define PRCMU_TIMER_REF 0
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#define PRCMU_TIMER_DOWNCOUNT 0x4
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#define PRCMU_TIMER_MODE 0x8
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static void __iomem *clksrc_dbx500_timer_base;
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static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs)
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{
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void __iomem *base = clksrc_dbx500_timer_base;
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u32 count, count2;
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do {
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count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
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count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
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} while (count2 != count);
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/* Negate because the timer is a decrementing counter */
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return ~count;
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}
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static struct clocksource clocksource_dbx500_prcmu = {
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.name = "dbx500-prcmu-timer",
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.rating = 100,
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.read = clksrc_dbx500_prcmu_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
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};
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static int __init clksrc_dbx500_prcmu_init(struct device_node *node)
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{
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clksrc_dbx500_timer_base = of_iomap(node, 0);
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/*
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* The A9 sub system expects the timer to be configured as
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* a continous looping timer.
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* The PRCMU should configure it but if it for some reason
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* don't we do it here.
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*/
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if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
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TIMER_MODE_CONTINOUS) {
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writel(TIMER_MODE_CONTINOUS,
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clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
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writel(TIMER_DOWNCOUNT_VAL,
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clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
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}
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return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
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}
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TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
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clksrc_dbx500_prcmu_init);
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