forked from luck/tmp_suning_uos_patched
5ed0e74104
Add missing .owner field in ns2_pci_phy_ops, which is used for refcounting. While at it, also makes ns2_pci_phy_ops const as it's never get modified. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-and-tested-by: Jon Mason <jon.mason@broadcom.com> Reviewed-by: Pramod Kumar <pramodku@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
102 lines
2.5 KiB
C
102 lines
2.5 KiB
C
/*
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* Copyright (C) 2016 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/of_mdio.h>
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#include <linux/mdio.h>
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#include <linux/phy.h>
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#include <linux/phy/phy.h>
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#define BLK_ADDR_REG_OFFSET 0x1f
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#define PLL_AFE1_100MHZ_BLK 0x2100
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#define PLL_CLK_AMP_OFFSET 0x03
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#define PLL_CLK_AMP_2P05V 0x2b18
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static int ns2_pci_phy_init(struct phy *p)
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{
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struct mdio_device *mdiodev = phy_get_drvdata(p);
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int rc;
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/* select the AFE 100MHz block page */
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rc = mdiobus_write(mdiodev->bus, mdiodev->addr,
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BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK);
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if (rc)
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goto err;
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/* set the 100 MHz reference clock amplitude to 2.05 v */
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rc = mdiobus_write(mdiodev->bus, mdiodev->addr,
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PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V);
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if (rc)
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goto err;
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return 0;
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err:
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dev_err(&mdiodev->dev, "Error %d writing to phy\n", rc);
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return rc;
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}
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static const struct phy_ops ns2_pci_phy_ops = {
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.init = ns2_pci_phy_init,
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.owner = THIS_MODULE,
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};
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static int ns2_pci_phy_probe(struct mdio_device *mdiodev)
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{
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struct device *dev = &mdiodev->dev;
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struct phy_provider *provider;
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struct phy *phy;
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phy = devm_phy_create(dev, dev->of_node, &ns2_pci_phy_ops);
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if (IS_ERR(phy)) {
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dev_err(dev, "failed to create Phy\n");
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return PTR_ERR(phy);
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}
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phy_set_drvdata(phy, mdiodev);
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provider = devm_of_phy_provider_register(&phy->dev,
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of_phy_simple_xlate);
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if (IS_ERR(provider)) {
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dev_err(dev, "failed to register Phy provider\n");
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return PTR_ERR(provider);
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}
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dev_info(dev, "%s PHY registered\n", dev_name(dev));
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return 0;
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}
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static const struct of_device_id ns2_pci_phy_of_match[] = {
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{ .compatible = "brcm,ns2-pcie-phy", },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, ns2_pci_phy_of_match);
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static struct mdio_driver ns2_pci_phy_driver = {
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.mdiodrv = {
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.driver = {
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.name = "phy-bcm-ns2-pci",
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.of_match_table = ns2_pci_phy_of_match,
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},
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},
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.probe = ns2_pci_phy_probe,
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};
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mdio_module_driver(ns2_pci_phy_driver);
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MODULE_AUTHOR("Broadcom");
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MODULE_DESCRIPTION("Broadcom Northstar2 PCI Phy driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:phy-bcm-ns2-pci");
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