forked from luck/tmp_suning_uos_patched
4743765bab
On Cherry Trail devices under Windows the PWM controller used for the backlight is considered part of the GPU even though it is part of the LPSS block and thus is an entirely different independent hardware unit. Because of this on Cherry Trail the GPU's (GFX0 ACPI node) _PS3 and _PS0 methods save and restore the PWM controller registers. If userspace blanks the screen before suspending, such as e.g. GNOME does, then the PWM controller will be runtime-suspended when the suspend starts. This causes the GFX0 _PS? methods to save a value of 0xffffffff for the PWM control register and to restore this value on resume. 0xffffffff is not a valid value for the register and writing this causes problems such as e.g. a flickering backlight. This commit adds a prepare method to the dev_pm_ops and makes it return 0 on Cherry Trail devices forcing a runtime-resume before other device's suspend methods run. This fixes the reading and writing back of 0xffffffff. Since we now always runtime-resume the device on suspend, it will be resumed on resume too and we no longer need to check for the GFX0 _PS0 method having resumed it underneath us, so this commit removes the now no longer necessary complete dev_pm_op. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
47 lines
1.1 KiB
C
47 lines
1.1 KiB
C
/*
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* Intel Low Power Subsystem PWM controller driver
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*
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* Copyright (C) 2014, Intel Corporation
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*
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* Derived from the original pwm-lpss.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PWM_LPSS_H
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#define __PWM_LPSS_H
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#include <linux/device.h>
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#include <linux/pwm.h>
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#define MAX_PWMS 4
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struct pwm_lpss_chip {
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struct pwm_chip chip;
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void __iomem *regs;
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const struct pwm_lpss_boardinfo *info;
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u32 saved_ctrl[MAX_PWMS];
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};
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struct pwm_lpss_boardinfo {
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unsigned long clk_rate;
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unsigned int npwm;
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unsigned long base_unit_bits;
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bool bypass;
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/*
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* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
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* messes with the PWM0 controllers state,
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*/
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bool other_devices_aml_touches_pwm_regs;
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};
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struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
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const struct pwm_lpss_boardinfo *info);
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int pwm_lpss_remove(struct pwm_lpss_chip *lpwm);
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int pwm_lpss_suspend(struct device *dev);
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int pwm_lpss_resume(struct device *dev);
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#endif /* __PWM_LPSS_H */
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