forked from luck/tmp_suning_uos_patched
0cd61b68c3
Untested, but this should fix up the bulk of the totally mechanical issues, and should make the actual detail fixing easier. Signed-off-by: Linus Torvalds <torvalds@osdl.org>
70 lines
1.3 KiB
C
70 lines
1.3 KiB
C
/*
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* linux/arch/arm/mach-footbridge/dc21285-timer.c
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*
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* Copyright (C) 1998 Russell King.
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* Copyright (C) 1998 Phil Blundell
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq.h>
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#include <asm/hardware/dec21285.h>
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#include <asm/mach/time.h>
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#include "common.h"
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/*
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* Footbridge timer 1 support.
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*/
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static unsigned long timer1_latch;
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static unsigned long timer1_gettimeoffset (void)
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{
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unsigned long value = timer1_latch - *CSR_TIMER1_VALUE;
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return ((tick_nsec / 1000) * value) / timer1_latch;
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}
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static irqreturn_t
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timer1_interrupt(int irq, void *dev_id)
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{
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write_seqlock(&xtime_lock);
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*CSR_TIMER1_CLR = 0;
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timer_tick();
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction footbridge_timer_irq = {
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.name = "Timer1 timer tick",
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.handler = timer1_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER,
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};
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/*
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* Set up timer interrupt.
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*/
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static void __init footbridge_timer_init(void)
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{
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timer1_latch = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
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*CSR_TIMER1_CLR = 0;
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*CSR_TIMER1_LOAD = timer1_latch;
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*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | TIMER_CNTL_DIV16;
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setup_irq(IRQ_TIMER1, &footbridge_timer_irq);
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isa_rtc_init();
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}
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struct sys_timer footbridge_timer = {
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.init = footbridge_timer_init,
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.offset = timer1_gettimeoffset,
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};
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