forked from luck/tmp_suning_uos_patched
44d1b980c7
Although if people have questions about ARCnet, perhaps it's _better_ for them to be mailing dwmw2@cam.ac.uk about it... Signed-off-by: David Woodhouse <dwmw2@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
190 lines
4.6 KiB
ArmAsm
190 lines
4.6 KiB
ArmAsm
/* cmode.S: clock mode management
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Woodhouse (dwmw2@infradead.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/ptrace.h>
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#include <asm/errno.h>
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#include <asm/cache.h>
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#include <asm/spr-regs.h>
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#define __addr_MASK 0xfeff9820 /* interrupt controller mask */
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#define __addr_SDRAMC 0xfe000400 /* SDRAM controller regs */
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#define SDRAMC_DSTS 0x28 /* SDRAM status */
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#define SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
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#define SDRAMC_DRCN 0x30 /* SDRAM refresh control */
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#define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
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#define __addr_CLKC 0xfeff9a00
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#define CLKC_SWCMODE 0x00000008
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#define __addr_LEDS 0xe1200004
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.macro li v r
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sethi.p %hi(\v),\r
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setlo %lo(\v),\r
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.endm
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.text
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.balign 4
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###############################################################################
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#
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# Change CMODE
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# - void frv_change_cmode(int cmode)
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#
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###############################################################################
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.globl frv_change_cmode
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.type frv_change_cmode,@function
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.macro LEDS v
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#ifdef DEBUG_CMODE
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setlos #~\v,gr10
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sti gr10,@(gr11,#0)
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membar
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#endif
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.endm
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frv_change_cmode:
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movsg lr,gr9
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#ifdef DEBUG_CMODE
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li __addr_LEDS,gr11
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#endif
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dcef @(gr0,gr0),#1
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# Shift argument left by 24 bits to fit in SWCMODE register later.
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slli gr8,#24,gr8
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# (1) Set '0' in the PSR.ET bit, and prohibit interrupts.
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movsg psr,gr14
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andi gr14,#~PSR_ET,gr3
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movgs gr3,psr
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#if 0 // Fujitsu recommend to skip this and will update docs.
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# (2) Set '0' to all bits of the MASK register of the interrupt
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# controller, and mask interrupts.
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li __addr_MASK,gr12
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ldi @(gr12,#0),gr13
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li 0xffff0000,gr4
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sti gr4,@(gr12,#0)
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#endif
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# (3) Stop the transfer function of DMAC. Stop all the bus masters
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# to access SDRAM and the internal resources.
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# (already done by caller)
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# (4) Preload a series of following instructions to the instruction
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# cache.
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li #__cmode_icache_lock_start,gr3
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li #__cmode_icache_lock_end,gr4
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1: icpl gr3,gr0,#1
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addi gr3,#L1_CACHE_BYTES,gr3
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cmp gr4,gr3,icc0
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bhi icc0,#0,1b
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# Set up addresses in regs for later steps.
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setlos SDRAMC_DRCN_SR,gr3
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li __addr_SDRAMC,gr4
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li __addr_CLKC,gr5
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ldi @(gr5,#0),gr6
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li #0x80000000,gr7
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or gr6,gr7,gr6
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bra __cmode_icache_lock_start
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.balign L1_CACHE_BYTES
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__cmode_icache_lock_start:
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# (5) Flush the content of all caches by the DCEF instruction.
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dcef @(gr0,gr0),#1
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# (6) Execute loading the dummy for SDRAM.
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ldi @(gr9,#0),gr0
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# (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
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# self-refresh mode. Execute the dummy load to all memory
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# devices set to cacheable on the external bus side in parallel
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# with this.
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sti gr3,@(gr4,#SDRAMC_DRCN)
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# (8) Execute memory barrier instruction (MEMBAR).
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membar
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# (9) Read the DSTS register repeatedly until '1' stands in the
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# DSTS.SSI field.
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1: ldi @(gr4,#SDRAMC_DSTS),gr3
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andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0
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beq icc0,#0,1b
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# (10) Execute memory barrier instruction (MEMBAR).
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membar
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#if 1
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# (11) Set the value of CMODE that you want to change to
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# SWCMODE.SWCM[3:0].
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sti gr8,@(gr5,#CLKC_SWCMODE)
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# (12) Set '1' to the CLKC.SWEN bit. In that case, do not change
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# fields other than SWEN of the CLKC register.
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sti gr6,@(gr5,#0)
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#endif
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# (13) Execute the instruction just after the memory barrier
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# instruction that executes the self-loop 256 times. (Meanwhile,
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# the CMODE switch is done.)
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membar
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setlos #256,gr7
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2: subicc gr7,#1,gr7,icc0
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bne icc0,#2,2b
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LEDS 0x36
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# (14) Release the self-refresh of SDRAM.
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sti gr0,@(gr4,#SDRAMC_DRCN)
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# Wait for it...
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3: ldi @(gr4,#SDRAMC_DSTS),gr3
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andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0
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bne icc0,#2,3b
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#if 0
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li 0x0100000,gr10
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4: subicc gr10,#1,gr10,icc0
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bne icc0,#0,4b
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#endif
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__cmode_icache_lock_end:
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li #__cmode_icache_lock_start,gr3
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li #__cmode_icache_lock_end,gr4
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4: icul gr3
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addi gr3,#L1_CACHE_BYTES,gr3
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cmp gr4,gr3,icc0
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bhi icc0,#0,4b
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#if 0 // Fujitsu recommend to skip this and will update docs.
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# (15) Release the interrupt mask setting of the MASK register of
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# the interrupt controller if necessary.
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sti gr13,@(gr12,#0)
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#endif
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# (16) Set 1' in the PSR.ET bit, and permit interrupt.
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movgs gr14,psr
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bralr
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.size frv_change_cmode, .-frv_change_cmode
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