forked from luck/tmp_suning_uos_patched
013de2d667
This patch adds files related to memory management and here is our memory-layout: Fixmap : 0xffc02000 – 0xfffff000 (4 MB - 12KB) Pkmap : 0xff800000 – 0xffc00000 (4 MB) Vmalloc : 0xf0200000 – 0xff000000 (238 MB) Lowmem : 0x80000000 – 0xc0000000 (1GB) abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem. abiv2 CPUs are all PIPT cache and they could support highmem. Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup memory page table for it. Link:https://lore.kernel.org/lkml/20180518215548.GH17671@n2100.armlinux.org.uk/ Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Christoph Hellwig <hch@infradead.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
255 lines
5.8 KiB
C
255 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/cache.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-contiguous.h>
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#include <linux/dma-noncoherent.h>
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#include <linux/genalloc.h>
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#include <linux/highmem.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/scatterlist.h>
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#include <linux/types.h>
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#include <linux/version.h>
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#include <asm/cache.h>
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static struct gen_pool *atomic_pool;
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static size_t atomic_pool_size __initdata = SZ_256K;
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static int __init early_coherent_pool(char *p)
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{
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atomic_pool_size = memparse(p, &p);
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return 0;
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}
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early_param("coherent_pool", early_coherent_pool);
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static int __init atomic_pool_init(void)
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{
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struct page *page;
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size_t size = atomic_pool_size;
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void *ptr;
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int ret;
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atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
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if (!atomic_pool)
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BUG();
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page = alloc_pages(GFP_KERNEL | GFP_DMA, get_order(size));
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if (!page)
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BUG();
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ptr = dma_common_contiguous_remap(page, size, VM_ALLOC,
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pgprot_noncached(PAGE_KERNEL),
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__builtin_return_address(0));
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if (!ptr)
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BUG();
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ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
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page_to_phys(page), atomic_pool_size, -1);
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if (ret)
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BUG();
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gen_pool_set_algo(atomic_pool, gen_pool_first_fit_order_align, NULL);
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pr_info("DMA: preallocated %zu KiB pool for atomic coherent pool\n",
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atomic_pool_size / 1024);
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pr_info("DMA: vaddr: 0x%x phy: 0x%lx,\n", (unsigned int)ptr,
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page_to_phys(page));
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return 0;
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}
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postcore_initcall(atomic_pool_init);
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static void *csky_dma_alloc_atomic(struct device *dev, size_t size,
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dma_addr_t *dma_handle)
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{
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unsigned long addr;
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addr = gen_pool_alloc(atomic_pool, size);
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if (addr)
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*dma_handle = gen_pool_virt_to_phys(atomic_pool, addr);
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return (void *)addr;
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}
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static void csky_dma_free_atomic(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle, unsigned long attrs)
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{
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gen_pool_free(atomic_pool, (unsigned long)vaddr, size);
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}
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static void __dma_clear_buffer(struct page *page, size_t size)
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{
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if (PageHighMem(page)) {
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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do {
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void *ptr = kmap_atomic(page);
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size_t _size = (size < PAGE_SIZE) ? size : PAGE_SIZE;
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memset(ptr, 0, _size);
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dma_wbinv_range((unsigned long)ptr,
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(unsigned long)ptr + _size);
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kunmap_atomic(ptr);
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page++;
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size -= PAGE_SIZE;
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count--;
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} while (count);
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} else {
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void *ptr = page_address(page);
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memset(ptr, 0, size);
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dma_wbinv_range((unsigned long)ptr, (unsigned long)ptr + size);
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}
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}
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static void *csky_dma_alloc_nonatomic(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp,
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unsigned long attrs)
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{
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void *vaddr;
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struct page *page;
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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if (DMA_ATTR_NON_CONSISTENT & attrs) {
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pr_err("csky %s can't support DMA_ATTR_NON_CONSISTENT.\n", __func__);
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return NULL;
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}
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if (IS_ENABLED(CONFIG_DMA_CMA))
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page = dma_alloc_from_contiguous(dev, count, get_order(size),
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gfp);
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else
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page = alloc_pages(gfp, get_order(size));
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if (!page) {
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pr_err("csky %s no more free pages.\n", __func__);
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return NULL;
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}
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*dma_handle = page_to_phys(page);
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__dma_clear_buffer(page, size);
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if (attrs & DMA_ATTR_NO_KERNEL_MAPPING)
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return page;
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vaddr = dma_common_contiguous_remap(page, PAGE_ALIGN(size), VM_USERMAP,
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pgprot_noncached(PAGE_KERNEL), __builtin_return_address(0));
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if (!vaddr)
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BUG();
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return vaddr;
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}
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static void csky_dma_free_nonatomic(
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struct device *dev,
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size_t size,
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void *vaddr,
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dma_addr_t dma_handle,
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unsigned long attrs
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)
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{
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struct page *page = phys_to_page(dma_handle);
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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if ((unsigned int)vaddr >= VMALLOC_START)
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dma_common_free_remap(vaddr, size, VM_USERMAP);
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if (IS_ENABLED(CONFIG_DMA_CMA))
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dma_release_from_contiguous(dev, page, count);
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else
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__free_pages(page, get_order(size));
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}
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void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t gfp, unsigned long attrs)
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{
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if (gfpflags_allow_blocking(gfp))
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return csky_dma_alloc_nonatomic(dev, size, dma_handle, gfp,
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attrs);
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else
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return csky_dma_alloc_atomic(dev, size, dma_handle);
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}
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void arch_dma_free(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle, unsigned long attrs)
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{
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if (!addr_in_gen_pool(atomic_pool, (unsigned int) vaddr, size))
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csky_dma_free_nonatomic(dev, size, vaddr, dma_handle, attrs);
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else
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csky_dma_free_atomic(dev, size, vaddr, dma_handle, attrs);
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}
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static inline void cache_op(phys_addr_t paddr, size_t size,
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void (*fn)(unsigned long start, unsigned long end))
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{
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struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
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unsigned int offset = paddr & ~PAGE_MASK;
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size_t left = size;
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unsigned long start;
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do {
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size_t len = left;
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if (PageHighMem(page)) {
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void *addr;
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if (offset + len > PAGE_SIZE) {
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if (offset >= PAGE_SIZE) {
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page += offset >> PAGE_SHIFT;
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offset &= ~PAGE_MASK;
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}
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len = PAGE_SIZE - offset;
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}
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addr = kmap_atomic(page);
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start = (unsigned long)(addr + offset);
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fn(start, start + len);
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kunmap_atomic(addr);
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} else {
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start = (unsigned long)phys_to_virt(paddr);
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fn(start, start + size);
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}
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offset = 0;
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page++;
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left -= len;
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} while (left);
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}
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void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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cache_op(paddr, size, dma_wb_range);
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break;
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL:
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cache_op(paddr, size, dma_wbinv_range);
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break;
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default:
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BUG();
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}
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}
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void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
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size_t size, enum dma_data_direction dir)
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{
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switch (dir) {
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case DMA_TO_DEVICE:
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cache_op(paddr, size, dma_wb_range);
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break;
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case DMA_FROM_DEVICE:
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case DMA_BIDIRECTIONAL:
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cache_op(paddr, size, dma_wbinv_range);
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break;
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default:
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BUG();
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}
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}
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