forked from luck/tmp_suning_uos_patched
e2f91578b3
Tegra2 hangs if APB registers are accessed from the cpu during an apb dma operation. The workaround is to use apb dma to read/write the registers instead. There is a dependency loop between fuses, clocks, and APBDMA. If dma is enabled, fuse reads must go through APBDMA to avoid corruption due to a hw bug. APBDMA requires a clock to be enabled. Clocks must read a fuse to determine allowable cpu frequencies. Separate out the fuse DMA initialization, and allow the fuse read and write functions to be called without using DMA before the DMA initialization has been completed. Access to the fuses before APBDMA is initialized won't hit the hardware bug because nothing else can be using DMA. Original fuse registar access code from Varun Wadekar <vwadekar@nvidia.com>, improved by Colin Cross <ccross@android.com> and later moved to separate driver by Jon Mayo <jmayo@nvidia.com>. Major refactoring/cleanup by Olof Johansson <olof@lixom.net>. Changes since v1: * fix 'return false' on error condition * dequeue dma ops in case of timeout From: Jon Mayo <jmayo@nvidia.com>. Signed-off-by: Jon Mayo <jmayo@nvidia.com>. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com>
146 lines
3.3 KiB
C
146 lines
3.3 KiB
C
/*
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* Copyright (C) 2010 NVIDIA Corporation.
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include <linux/completion.h>
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#include <linux/sched.h>
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#include <linux/mutex.h>
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#include <mach/dma.h>
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#include <mach/iomap.h>
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#include "apbio.h"
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static DEFINE_MUTEX(tegra_apb_dma_lock);
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static struct tegra_dma_channel *tegra_apb_dma;
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static u32 *tegra_apb_bb;
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static dma_addr_t tegra_apb_bb_phys;
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static DECLARE_COMPLETION(tegra_apb_wait);
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bool tegra_apb_init(void)
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{
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struct tegra_dma_channel *ch;
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mutex_lock(&tegra_apb_dma_lock);
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/* Check to see if we raced to setup */
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if (tegra_apb_dma)
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goto out;
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ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
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TEGRA_DMA_SHARED);
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if (!ch)
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goto out_fail;
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tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
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&tegra_apb_bb_phys, GFP_KERNEL);
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if (!tegra_apb_bb) {
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pr_err("%s: can not allocate bounce buffer\n", __func__);
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tegra_dma_free_channel(ch);
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goto out_fail;
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}
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tegra_apb_dma = ch;
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out:
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mutex_unlock(&tegra_apb_dma_lock);
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return true;
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out_fail:
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mutex_unlock(&tegra_apb_dma_lock);
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return false;
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}
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static void apb_dma_complete(struct tegra_dma_req *req)
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{
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complete(&tegra_apb_wait);
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}
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u32 tegra_apb_readl(unsigned long offset)
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{
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struct tegra_dma_req req;
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int ret;
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if (!tegra_apb_dma && !tegra_apb_init())
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return readl(IO_TO_VIRT(offset));
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mutex_lock(&tegra_apb_dma_lock);
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req.complete = apb_dma_complete;
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req.to_memory = 1;
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req.dest_addr = tegra_apb_bb_phys;
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req.dest_bus_width = 32;
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req.dest_wrap = 1;
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req.source_addr = offset;
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req.source_bus_width = 32;
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req.source_wrap = 4;
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req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
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req.size = 4;
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INIT_COMPLETION(tegra_apb_wait);
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tegra_dma_enqueue_req(tegra_apb_dma, &req);
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ret = wait_for_completion_timeout(&tegra_apb_wait,
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msecs_to_jiffies(50));
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if (WARN(ret == 0, "apb read dma timed out")) {
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tegra_dma_dequeue_req(tegra_apb_dma, &req);
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*(u32 *)tegra_apb_bb = 0;
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}
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mutex_unlock(&tegra_apb_dma_lock);
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return *((u32 *)tegra_apb_bb);
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}
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void tegra_apb_writel(u32 value, unsigned long offset)
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{
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struct tegra_dma_req req;
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int ret;
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if (!tegra_apb_dma && !tegra_apb_init()) {
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writel(value, IO_TO_VIRT(offset));
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return;
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}
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mutex_lock(&tegra_apb_dma_lock);
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*((u32 *)tegra_apb_bb) = value;
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req.complete = apb_dma_complete;
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req.to_memory = 0;
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req.dest_addr = offset;
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req.dest_wrap = 4;
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req.dest_bus_width = 32;
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req.source_addr = tegra_apb_bb_phys;
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req.source_bus_width = 32;
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req.source_wrap = 1;
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req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
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req.size = 4;
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INIT_COMPLETION(tegra_apb_wait);
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tegra_dma_enqueue_req(tegra_apb_dma, &req);
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ret = wait_for_completion_timeout(&tegra_apb_wait,
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msecs_to_jiffies(50));
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if (WARN(ret == 0, "apb write dma timed out"))
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tegra_dma_dequeue_req(tegra_apb_dma, &req);
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mutex_unlock(&tegra_apb_dma_lock);
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}
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