forked from luck/tmp_suning_uos_patched
9465a54fa4
Support the SH7712 (SH3-DSP) Solution Engine reference board. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
104 lines
2.5 KiB
C
104 lines
2.5 KiB
C
/*
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* SH7710 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <asm/sci.h>
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xa4400000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 52, 53, 55, 54 },
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}, {
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.mapbase = 0xa4420000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 56, 57, 59, 58 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct platform_device *sh7710_devices[] __initdata = {
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&sci_device,
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};
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static int __init sh7710_devices_setup(void)
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{
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return platform_add_devices(sh7710_devices,
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ARRAY_SIZE(sh7710_devices));
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}
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__initcall(sh7710_devices_setup);
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static struct ipr_data sh7710_ipr_map[] = {
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/* IRQ, IPR-idx, shift, priority */
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{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
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{ 17, 0, 8, 2 }, /* TMU1 TUNI */
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{ 18, 0, 4, 2 }, /* TMU2 TUNI */
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{ 27, 1, 12, 2 }, /* WDT ITI */
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{ 20, 0, 0, 2 }, /* RTC ATI (alarm) */
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{ 21, 0, 0, 2 }, /* RTC PRI (period) */
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{ 22, 0, 0, 2 }, /* RTC CUI (carry) */
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{ 48, 4, 12, 7 }, /* DMAC DMTE0 */
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{ 49, 4, 12, 7 }, /* DMAC DMTE1 */
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{ 50, 4, 12, 7 }, /* DMAC DMTE2 */
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{ 51, 4, 12, 7 }, /* DMAC DMTE3 */
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{ 52, 4, 8, 3 }, /* SCIF0 ERI */
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{ 53, 4, 8, 3 }, /* SCIF0 RXI */
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{ 54, 4, 8, 3 }, /* SCIF0 BRI */
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{ 55, 4, 8, 3 }, /* SCIF0 TXI */
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{ 56, 4, 4, 3 }, /* SCIF1 ERI */
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{ 57, 4, 4, 3 }, /* SCIF1 RXI */
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{ 58, 4, 4, 3 }, /* SCIF1 BRI */
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{ 59, 4, 4, 3 }, /* SCIF1 TXI */
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{ 76, 5, 8, 7 }, /* DMAC DMTE4 */
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{ 77, 5, 8, 7 }, /* DMAC DMTE5 */
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{ 80, 6, 12, 5 }, /* EDMAC EINT0 */
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{ 81, 6, 8, 5 }, /* EDMAC EINT1 */
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{ 82, 6, 4, 5 }, /* EDMAC EINT2 */
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};
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static unsigned long ipr_offsets[] = {
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0xA414FEE2 /* 0: IPRA */
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, 0xA414FEE4 /* 1: IPRB */
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, 0xA4140016 /* 2: IPRC */
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, 0xA4140018 /* 3: IPRD */
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, 0xA414001A /* 4: IPRE */
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, 0xA4080000 /* 5: IPRF */
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, 0xA4080002 /* 6: IPRG */
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, 0xA4080004 /* 7: IPRH */
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, 0xA4080006 /* 8: IPRI */
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};
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/* given the IPR index return the address of the IPR register */
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unsigned int map_ipridx_to_addr(int idx)
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{
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if (idx >= ARRAY_SIZE(ipr_offsets))
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return 0;
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return ipr_offsets[idx];
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}
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void __init init_IRQ_ipr()
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{
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make_ipr_irq(sh7710_ipr_map, ARRAY_SIZE(sh7710_ipr_map));
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}
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