forked from luck/tmp_suning_uos_patched
d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
50 lines
2.0 KiB
C
50 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Interrupt handler for OMAP-1510 FPGA
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*
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* Copyright (C) 2001 RidgeRun, Inc.
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* Author: Greg Lonnon <glonnon@ridgerun.com>
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*
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* Copyright (C) 2002 MontaVista Software, Inc.
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*
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* Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
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* Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
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*/
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#ifndef __ASM_ARCH_OMAP_FPGA_H
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#define __ASM_ARCH_OMAP_FPGA_H
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/*
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* ---------------------------------------------------------------------------
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* H2/P2 Debug board FPGA
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* ---------------------------------------------------------------------------
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*/
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/* maps in the FPGA registers and the ETHR registers */
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#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
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#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */
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#define H2P2_DBG_FPGA_START 0x04000000 /* PA */
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#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
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#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
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#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
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#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
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#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
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#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
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#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
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#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
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/* LEDs definition on debug board (16 LEDs, all physically green) */
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#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
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#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
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#define H2P2_DBG_FPGA_LED_RED (1 << 13)
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#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
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/* cpu0 load-meter LEDs */
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#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
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#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
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#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
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#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
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#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
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#endif
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