John Crispin 740c606e8e MIPS: lantiq: adds static clock for PP32 ... The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4815/		2013-02-17 00:15:17 +01:00
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clk.c	MIPS: lantiq: adds static clock for PP32	2013-02-17 00:15:17 +01:00
dma.c	MIPS: drivers: remove __dev* attributes.	2013-01-03 15:57:09 -08:00
gptu.c	MIPS: drivers: remove __dev* attributes.	2013-01-03 15:57:09 -08:00
Makefile	MIPS: lantiq: adds GPHY firmware loader	2012-11-11 18:47:41 +01:00
prom.c	MIPS: lantiq: add xway soc ids	2012-05-15 17:49:23 +02:00
reset.c	MIPS: lantiq: adds code for booting GPHY	2012-11-11 18:47:35 +01:00
sysctrl.c	MIPS: lantiq: adds static clock for PP32	2013-02-17 00:15:17 +01:00
xrx200_phy_fw.c	MIPS: drivers: remove __dev* attributes.	2013-01-03 15:57:09 -08:00