forked from luck/tmp_suning_uos_patched
80605c6513
Consolidate packet buffer allocation currently being done in the DCB path and main path. This allows the feature set and packet buffer requirements to be done once. This is prep work to allow DCB to coexist with other features namely, flow director. CC: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
321 lines
8.9 KiB
C
321 lines
8.9 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2011 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#include "ixgbe.h"
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#include "ixgbe_type.h"
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#include "ixgbe_dcb.h"
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#include "ixgbe_dcb_82598.h"
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#include "ixgbe_dcb_82599.h"
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/**
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* ixgbe_ieee_credits - This calculates the ieee traffic class
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* credits from the configured bandwidth percentages. Credits
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* are the smallest unit programmable into the underlying
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* hardware. The IEEE 802.1Qaz specification do not use bandwidth
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* groups so this is much simplified from the CEE case.
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*/
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s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill, __u16 *max, int max_frame)
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{
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int min_percent = 100;
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int min_credit, multiplier;
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int i;
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min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
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DCB_CREDIT_QUANTUM;
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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if (bw[i] < min_percent && bw[i])
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min_percent = bw[i];
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}
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multiplier = (min_credit / min_percent) + 1;
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/* Find out the hw credits for each TC */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL);
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if (val < min_credit)
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val = min_credit;
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refill[i] = val;
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max[i] = bw[i] ? (bw[i] * MAX_CREDIT)/100 : min_credit;
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}
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return 0;
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}
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/**
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* ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits
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* @ixgbe_dcb_config: Struct containing DCB settings.
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* @direction: Configuring either Tx or Rx.
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*
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* This function calculates the credits allocated to each traffic class.
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* It should be called only after the rules are checked by
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* ixgbe_dcb_check_config().
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*/
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s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *hw,
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struct ixgbe_dcb_config *dcb_config,
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int max_frame, u8 direction)
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{
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struct tc_bw_alloc *p;
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int min_credit;
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int min_multiplier;
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int min_percent = 100;
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s32 ret_val = 0;
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/* Initialization values default for Tx settings */
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u32 credit_refill = 0;
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u32 credit_max = 0;
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u16 link_percentage = 0;
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u8 bw_percent = 0;
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u8 i;
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if (dcb_config == NULL) {
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ret_val = DCB_ERR_CONFIG;
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goto out;
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}
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min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
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DCB_CREDIT_QUANTUM;
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/* Find smallest link percentage */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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p = &dcb_config->tc_config[i].path[direction];
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bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
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link_percentage = p->bwg_percent;
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link_percentage = (link_percentage * bw_percent) / 100;
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if (link_percentage && link_percentage < min_percent)
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min_percent = link_percentage;
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}
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/*
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* The ratio between traffic classes will control the bandwidth
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* percentages seen on the wire. To calculate this ratio we use
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* a multiplier. It is required that the refill credits must be
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* larger than the max frame size so here we find the smallest
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* multiplier that will allow all bandwidth percentages to be
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* greater than the max frame size.
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*/
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min_multiplier = (min_credit / min_percent) + 1;
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/* Find out the link percentage for each TC first */
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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p = &dcb_config->tc_config[i].path[direction];
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bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
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link_percentage = p->bwg_percent;
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/* Must be careful of integer division for very small nums */
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link_percentage = (link_percentage * bw_percent) / 100;
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if (p->bwg_percent > 0 && link_percentage == 0)
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link_percentage = 1;
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/* Save link_percentage for reference */
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p->link_percent = (u8)link_percentage;
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/* Calculate credit refill ratio using multiplier */
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credit_refill = min(link_percentage * min_multiplier,
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MAX_CREDIT_REFILL);
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p->data_credits_refill = (u16)credit_refill;
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/* Calculate maximum credit for the TC */
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credit_max = (link_percentage * MAX_CREDIT) / 100;
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/*
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* Adjustment based on rule checking, if the percentage
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* of a TC is too small, the maximum credit may not be
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* enough to send out a jumbo frame in data plane arbitration.
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*/
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if (credit_max && (credit_max < min_credit))
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credit_max = min_credit;
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if (direction == DCB_TX_CONFIG) {
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/*
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* Adjustment based on rule checking, if the
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* percentage of a TC is too small, the maximum
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* credit may not be enough to send out a TSO
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* packet in descriptor plane arbitration.
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*/
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if ((hw->mac.type == ixgbe_mac_82598EB) &&
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credit_max &&
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(credit_max < MINIMUM_CREDIT_FOR_TSO))
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credit_max = MINIMUM_CREDIT_FOR_TSO;
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dcb_config->tc_config[i].desc_credits_max =
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(u16)credit_max;
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}
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p->data_credits_max = (u16)credit_max;
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}
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out:
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return ret_val;
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}
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void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en)
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{
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int i;
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*pfc_en = 0;
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
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*pfc_en |= (cfg->tc_config[i].dcb_pfc & 0xF) << i;
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}
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void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *cfg, int direction,
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u16 *refill)
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{
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struct tc_bw_alloc *p;
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int i;
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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p = &cfg->tc_config[i].path[direction];
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refill[i] = p->data_credits_refill;
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}
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}
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void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *cfg, u16 *max)
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{
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int i;
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
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max[i] = cfg->tc_config[i].desc_credits_max;
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}
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void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *cfg, int direction,
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u8 *bwgid)
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{
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struct tc_bw_alloc *p;
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int i;
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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p = &cfg->tc_config[i].path[direction];
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bwgid[i] = p->bwg_id;
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}
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}
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void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *cfg, int direction,
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u8 *ptype)
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{
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struct tc_bw_alloc *p;
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int i;
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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p = &cfg->tc_config[i].path[direction];
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ptype[i] = p->prio_type;
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}
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}
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/**
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* ixgbe_dcb_hw_config - Config and enable DCB
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure dcb settings and enable dcb mode.
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*/
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s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
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struct ixgbe_dcb_config *dcb_config)
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{
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s32 ret = 0;
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u8 pfc_en;
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u8 ptype[MAX_TRAFFIC_CLASS];
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u8 bwgid[MAX_TRAFFIC_CLASS];
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u16 refill[MAX_TRAFFIC_CLASS];
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u16 max[MAX_TRAFFIC_CLASS];
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/* CEE does not define a priority to tc mapping so map 1:1 */
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u8 prio_tc[MAX_TRAFFIC_CLASS] = {0, 1, 2, 3, 4, 5, 6, 7};
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/* Unpack CEE standard containers */
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ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en);
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ixgbe_dcb_unpack_refill(dcb_config, DCB_TX_CONFIG, refill);
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ixgbe_dcb_unpack_max(dcb_config, max);
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ixgbe_dcb_unpack_bwgid(dcb_config, DCB_TX_CONFIG, bwgid);
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ixgbe_dcb_unpack_prio(dcb_config, DCB_TX_CONFIG, ptype);
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switch (hw->mac.type) {
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case ixgbe_mac_82598EB:
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ret = ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max,
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bwgid, ptype);
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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ret = ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
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bwgid, ptype, prio_tc);
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break;
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default:
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break;
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}
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return ret;
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}
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/* Helper routines to abstract HW specifics from DCB netlink ops */
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s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en)
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{
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int ret = -EINVAL;
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switch (hw->mac.type) {
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case ixgbe_mac_82598EB:
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ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en);
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break;
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default:
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break;
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}
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return ret;
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}
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s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
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u16 *refill, u16 *max, u8 *bwg_id,
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u8 *prio_type, u8 *prio_tc)
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{
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switch (hw->mac.type) {
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case ixgbe_mac_82598EB:
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ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max,
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prio_type);
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ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
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bwg_id, prio_type);
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ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
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bwg_id, prio_type);
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
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bwg_id, prio_type, prio_tc);
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ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
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bwg_id, prio_type);
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ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
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prio_type, prio_tc);
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break;
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default:
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break;
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}
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return 0;
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}
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