forked from luck/tmp_suning_uos_patched
e5ba1c024a
commit e47d925 (usb: move the OTG state from
the USB PHY to the OTG structure) moved the
OTG state from struct usb_phy to struct usb_otg.
Unfortunately, even though I fixed quite a few
build regressions with that patch already, this
one was still missing.
Note that this driver still has other randconfig
build problems which I'll leave for driver author
to fix, as that's less trivial.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
407 lines
14 KiB
C
407 lines
14 KiB
C
/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/usb/otg-fsm.h>
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#include <linux/usb/otg.h>
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#include <linux/ioctl.h>
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/* USB Command Register Bit Masks */
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#define USB_CMD_RUN_STOP (0x1<<0)
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#define USB_CMD_CTRL_RESET (0x1<<1)
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#define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4)
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#define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5)
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#define USB_CMD_INT_AA_DOORBELL (0x1<<6)
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#define USB_CMD_ASP (0x3<<8)
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#define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11)
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#define USB_CMD_SUTW (0x1<<13)
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#define USB_CMD_ATDTW (0x1<<14)
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#define USB_CMD_ITC (0xFF<<16)
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/* bit 15,3,2 are frame list size */
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#define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2)
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#define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2)
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#define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2)
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#define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2)
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#define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2)
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#define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2)
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#define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2)
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#define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2)
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/* bit 9-8 are async schedule park mode count */
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#define USB_CMD_ASP_00 (0x0<<8)
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#define USB_CMD_ASP_01 (0x1<<8)
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#define USB_CMD_ASP_10 (0x2<<8)
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#define USB_CMD_ASP_11 (0x3<<8)
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#define USB_CMD_ASP_BIT_POS (8)
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/* bit 23-16 are interrupt threshold control */
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#define USB_CMD_ITC_NO_THRESHOLD (0x00<<16)
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#define USB_CMD_ITC_1_MICRO_FRM (0x01<<16)
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#define USB_CMD_ITC_2_MICRO_FRM (0x02<<16)
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#define USB_CMD_ITC_4_MICRO_FRM (0x04<<16)
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#define USB_CMD_ITC_8_MICRO_FRM (0x08<<16)
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#define USB_CMD_ITC_16_MICRO_FRM (0x10<<16)
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#define USB_CMD_ITC_32_MICRO_FRM (0x20<<16)
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#define USB_CMD_ITC_64_MICRO_FRM (0x40<<16)
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#define USB_CMD_ITC_BIT_POS (16)
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/* USB Status Register Bit Masks */
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#define USB_STS_INT (0x1<<0)
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#define USB_STS_ERR (0x1<<1)
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#define USB_STS_PORT_CHANGE (0x1<<2)
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#define USB_STS_FRM_LST_ROLL (0x1<<3)
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#define USB_STS_SYS_ERR (0x1<<4)
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#define USB_STS_IAA (0x1<<5)
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#define USB_STS_RESET_RECEIVED (0x1<<6)
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#define USB_STS_SOF (0x1<<7)
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#define USB_STS_DCSUSPEND (0x1<<8)
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#define USB_STS_HC_HALTED (0x1<<12)
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#define USB_STS_RCL (0x1<<13)
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#define USB_STS_PERIODIC_SCHEDULE (0x1<<14)
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#define USB_STS_ASYNC_SCHEDULE (0x1<<15)
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/* USB Interrupt Enable Register Bit Masks */
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#define USB_INTR_INT_EN (0x1<<0)
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#define USB_INTR_ERR_INT_EN (0x1<<1)
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#define USB_INTR_PC_DETECT_EN (0x1<<2)
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#define USB_INTR_FRM_LST_ROLL_EN (0x1<<3)
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#define USB_INTR_SYS_ERR_EN (0x1<<4)
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#define USB_INTR_ASYN_ADV_EN (0x1<<5)
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#define USB_INTR_RESET_EN (0x1<<6)
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#define USB_INTR_SOF_EN (0x1<<7)
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#define USB_INTR_DEVICE_SUSPEND (0x1<<8)
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/* Device Address bit masks */
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#define USB_DEVICE_ADDRESS_MASK (0x7F<<25)
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#define USB_DEVICE_ADDRESS_BIT_POS (25)
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/* PORTSC Register Bit Masks,Only one PORT in OTG mode*/
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#define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0)
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#define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1)
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#define PORTSC_PORT_ENABLE (0x1<<2)
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#define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3)
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#define PORTSC_OVER_CURRENT_ACT (0x1<<4)
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#define PORTSC_OVER_CUURENT_CHG (0x1<<5)
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#define PORTSC_PORT_FORCE_RESUME (0x1<<6)
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#define PORTSC_PORT_SUSPEND (0x1<<7)
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#define PORTSC_PORT_RESET (0x1<<8)
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#define PORTSC_LINE_STATUS_BITS (0x3<<10)
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#define PORTSC_PORT_POWER (0x1<<12)
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#define PORTSC_PORT_INDICTOR_CTRL (0x3<<14)
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#define PORTSC_PORT_TEST_CTRL (0xF<<16)
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#define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20)
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#define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21)
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#define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22)
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#define PORTSC_PHY_LOW_POWER_SPD (0x1<<23)
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#define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24)
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#define PORTSC_PORT_SPEED_MASK (0x3<<26)
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#define PORTSC_TRANSCEIVER_WIDTH (0x1<<28)
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#define PORTSC_PHY_TYPE_SEL (0x3<<30)
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/* bit 11-10 are line status */
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#define PORTSC_LINE_STATUS_SE0 (0x0<<10)
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#define PORTSC_LINE_STATUS_JSTATE (0x1<<10)
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#define PORTSC_LINE_STATUS_KSTATE (0x2<<10)
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#define PORTSC_LINE_STATUS_UNDEF (0x3<<10)
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#define PORTSC_LINE_STATUS_BIT_POS (10)
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/* bit 15-14 are port indicator control */
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#define PORTSC_PIC_OFF (0x0<<14)
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#define PORTSC_PIC_AMBER (0x1<<14)
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#define PORTSC_PIC_GREEN (0x2<<14)
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#define PORTSC_PIC_UNDEF (0x3<<14)
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#define PORTSC_PIC_BIT_POS (14)
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/* bit 19-16 are port test control */
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#define PORTSC_PTC_DISABLE (0x0<<16)
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#define PORTSC_PTC_JSTATE (0x1<<16)
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#define PORTSC_PTC_KSTATE (0x2<<16)
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#define PORTSC_PTC_SEQNAK (0x3<<16)
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#define PORTSC_PTC_PACKET (0x4<<16)
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#define PORTSC_PTC_FORCE_EN (0x5<<16)
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#define PORTSC_PTC_BIT_POS (16)
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/* bit 27-26 are port speed */
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#define PORTSC_PORT_SPEED_FULL (0x0<<26)
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#define PORTSC_PORT_SPEED_LOW (0x1<<26)
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#define PORTSC_PORT_SPEED_HIGH (0x2<<26)
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#define PORTSC_PORT_SPEED_UNDEF (0x3<<26)
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#define PORTSC_SPEED_BIT_POS (26)
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/* bit 28 is parallel transceiver width for UTMI interface */
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#define PORTSC_PTW (0x1<<28)
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#define PORTSC_PTW_8BIT (0x0<<28)
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#define PORTSC_PTW_16BIT (0x1<<28)
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/* bit 31-30 are port transceiver select */
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#define PORTSC_PTS_UTMI (0x0<<30)
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#define PORTSC_PTS_ULPI (0x2<<30)
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#define PORTSC_PTS_FSLS_SERIAL (0x3<<30)
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#define PORTSC_PTS_BIT_POS (30)
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#define PORTSC_W1C_BITS \
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(PORTSC_CONNECT_STATUS_CHANGE | \
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PORTSC_PORT_EN_DIS_CHANGE | \
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PORTSC_OVER_CUURENT_CHG)
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/* OTG Status Control Register Bit Masks */
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#define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0)
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#define OTGSC_CTRL_VBUS_CHARGE (0x1<<1)
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#define OTGSC_CTRL_OTG_TERMINATION (0x1<<3)
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#define OTGSC_CTRL_DATA_PULSING (0x1<<4)
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#define OTGSC_CTRL_ID_PULL_EN (0x1<<5)
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#define OTGSC_HA_DATA_PULSE (0x1<<6)
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#define OTGSC_HA_BA (0x1<<7)
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#define OTGSC_STS_USB_ID (0x1<<8)
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#define OTGSC_STS_A_VBUS_VALID (0x1<<9)
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#define OTGSC_STS_A_SESSION_VALID (0x1<<10)
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#define OTGSC_STS_B_SESSION_VALID (0x1<<11)
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#define OTGSC_STS_B_SESSION_END (0x1<<12)
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#define OTGSC_STS_1MS_TOGGLE (0x1<<13)
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#define OTGSC_STS_DATA_PULSING (0x1<<14)
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#define OTGSC_INTSTS_USB_ID (0x1<<16)
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#define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17)
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#define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18)
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#define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19)
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#define OTGSC_INTSTS_B_SESSION_END (0x1<<20)
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#define OTGSC_INTSTS_1MS (0x1<<21)
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#define OTGSC_INTSTS_DATA_PULSING (0x1<<22)
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#define OTGSC_INTR_USB_ID_EN (0x1<<24)
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#define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25)
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#define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26)
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#define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27)
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#define OTGSC_INTR_B_SESSION_END_EN (0x1<<28)
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#define OTGSC_INTR_1MS_TIMER_EN (0x1<<29)
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#define OTGSC_INTR_DATA_PULSING_EN (0x1<<30)
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#define OTGSC_INTSTS_MASK (0x00ff0000)
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/* USB MODE Register Bit Masks */
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#define USB_MODE_CTRL_MODE_IDLE (0x0<<0)
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#define USB_MODE_CTRL_MODE_DEVICE (0x2<<0)
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#define USB_MODE_CTRL_MODE_HOST (0x3<<0)
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#define USB_MODE_CTRL_MODE_RSV (0x1<<0)
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#define USB_MODE_SETUP_LOCK_OFF (0x1<<3)
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#define USB_MODE_STREAM_DISABLE (0x1<<4)
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#define USB_MODE_ES (0x1<<2) /* Endian Select */
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/* control Register Bit Masks */
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#define USB_CTRL_IOENB (0x1<<2)
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#define USB_CTRL_ULPI_INT0EN (0x1<<0)
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/* BCSR5 */
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#define BCSR5_INT_USB (0x02)
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/* USB module clk cfg */
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#define SCCR_OFFS (0xA08)
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#define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */
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#define SCCR_USB_MPHCM_11 (0x00c00000)
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#define SCCR_USB_MPHCM_01 (0x00400000)
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#define SCCR_USB_MPHCM_10 (0x00800000)
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#define SCCR_USB_DRCM_11 (0x00300000)
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#define SCCR_USB_DRCM_01 (0x00100000)
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#define SCCR_USB_DRCM_10 (0x00200000)
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#define SICRL_OFFS (0x114)
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#define SICRL_USB0 (0x40000000)
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#define SICRL_USB1 (0x20000000)
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#define SICRH_OFFS (0x118)
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#define SICRH_USB_UTMI (0x00020000)
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/* OTG interrupt enable bit masks */
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#define OTGSC_INTERRUPT_ENABLE_BITS_MASK \
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(OTGSC_INTR_USB_ID_EN | \
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OTGSC_INTR_1MS_TIMER_EN | \
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OTGSC_INTR_A_VBUS_VALID_EN | \
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OTGSC_INTR_A_SESSION_VALID_EN | \
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OTGSC_INTR_B_SESSION_VALID_EN | \
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OTGSC_INTR_B_SESSION_END_EN | \
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OTGSC_INTR_DATA_PULSING_EN)
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/* OTG interrupt status bit masks */
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#define OTGSC_INTERRUPT_STATUS_BITS_MASK \
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(OTGSC_INTSTS_USB_ID | \
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OTGSC_INTR_1MS_TIMER_EN | \
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OTGSC_INTSTS_A_VBUS_VALID | \
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OTGSC_INTSTS_A_SESSION_VALID | \
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OTGSC_INTSTS_B_SESSION_VALID | \
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OTGSC_INTSTS_B_SESSION_END | \
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OTGSC_INTSTS_DATA_PULSING)
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/*
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* A-DEVICE timing constants
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*/
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/* Wait for VBUS Rise */
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#define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */
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/* Wait for B-Connect */
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#define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2
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* This is only used to get out of
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* OTG_STATE_A_WAIT_BCON state if there was
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* no connection for these many milliseconds
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*/
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/* A-Idle to B-Disconnect */
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/* It is necessary for this timer to be more than 750 ms because of a bug in OPT
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* test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
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* in the test description
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*/
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#define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */
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/* B-Idle to A-Disconnect */
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#define TA_BIDL_ADIS (12) /* 3 to 200 ms */
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/* B-device timing constants */
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/* Data-Line Pulse Time*/
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#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */
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#define TB_DATA_PLS_MIN (5) /* minimum 5 ms */
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#define TB_DATA_PLS_MAX (10) /* maximum 10 ms */
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/* SRP Initiate Time */
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#define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */
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/* SRP Fail Time */
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#define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/
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/* SRP result wait time */
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#define TB_SRP_WAIT (60)
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/* VBus time */
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#define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */
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/* Discharge time */
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/* This time should be less than 10ms. It varies from system to system. */
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#define TB_VBUS_DSCHRG (8)
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/* A-SE0 to B-Reset */
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#define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
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/* A bus suspend timer before we can switch to b_wait_aconn */
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#define TB_A_SUSPEND (7)
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#define TB_BUS_RESUME (12)
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/* SE0 Time Before SRP */
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#define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */
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#define SET_OTG_STATE(phy, newstate) ((phy)->otg->state = newstate)
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struct usb_dr_mmap {
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/* Capability register */
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u8 res1[256];
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u16 caplength; /* Capability Register Length */
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u16 hciversion; /* Host Controller Interface Version */
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u32 hcsparams; /* Host Controller Structual Parameters */
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u32 hccparams; /* Host Controller Capability Parameters */
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u8 res2[20];
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u32 dciversion; /* Device Controller Interface Version */
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u32 dccparams; /* Device Controller Capability Parameters */
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u8 res3[24];
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/* Operation register */
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u32 usbcmd; /* USB Command Register */
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u32 usbsts; /* USB Status Register */
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u32 usbintr; /* USB Interrupt Enable Register */
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u32 frindex; /* Frame Index Register */
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u8 res4[4];
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u32 deviceaddr; /* Device Address */
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u32 endpointlistaddr; /* Endpoint List Address Register */
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u8 res5[4];
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u32 burstsize; /* Master Interface Data Burst Size Register */
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u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
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u8 res6[8];
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u32 ulpiview; /* ULPI register access */
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u8 res7[12];
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u32 configflag; /* Configure Flag Register */
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u32 portsc; /* Port 1 Status and Control Register */
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u8 res8[28];
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u32 otgsc; /* On-The-Go Status and Control */
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u32 usbmode; /* USB Mode Register */
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u32 endptsetupstat; /* Endpoint Setup Status Register */
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u32 endpointprime; /* Endpoint Initialization Register */
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u32 endptflush; /* Endpoint Flush Register */
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u32 endptstatus; /* Endpoint Status Register */
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u32 endptcomplete; /* Endpoint Complete Register */
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u32 endptctrl[6]; /* Endpoint Control Registers */
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u8 res9[552];
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u32 snoop1;
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u32 snoop2;
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u32 age_cnt_thresh; /* Age Count Threshold Register */
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u32 pri_ctrl; /* Priority Control Register */
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u32 si_ctrl; /* System Interface Control Register */
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u8 res10[236];
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u32 control; /* General Purpose Control Register */
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};
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struct fsl_otg_timer {
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unsigned long expires; /* Number of count increase to timeout */
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unsigned long count; /* Tick counter */
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void (*function)(unsigned long); /* Timeout function */
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unsigned long data; /* Data passed to function */
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struct list_head list;
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};
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inline struct fsl_otg_timer *otg_timer_initializer
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(void (*function)(unsigned long), unsigned long expires, unsigned long data)
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{
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struct fsl_otg_timer *timer;
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timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
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if (!timer)
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return NULL;
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timer->function = function;
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timer->expires = expires;
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timer->data = data;
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return timer;
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}
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struct fsl_otg {
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struct usb_phy phy;
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struct otg_fsm fsm;
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struct usb_dr_mmap *dr_mem_map;
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struct delayed_work otg_event;
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/* used for usb host */
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struct work_struct work_wq;
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u8 host_working;
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int irq;
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};
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struct fsl_otg_config {
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u8 otg_port;
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};
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/* For SRP and HNP handle */
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#define FSL_OTG_MAJOR 240
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#define FSL_OTG_NAME "fsl-usb2-otg"
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/* Command to OTG driver ioctl */
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#define OTG_IOCTL_MAGIC FSL_OTG_MAJOR
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/* if otg work as host, it should return 1, otherwise return 0 */
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#define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int)
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#define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int)
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#define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int)
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#define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int)
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#define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int)
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#define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int)
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#define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int)
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#define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int)
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#define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int)
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void fsl_otg_add_timer(struct otg_fsm *fsm, void *timer);
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void fsl_otg_del_timer(struct otg_fsm *fsm, void *timer);
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void fsl_otg_pulse_vbus(void);
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