forked from luck/tmp_suning_uos_patched
c5db858bdf
This patch adds memory to memory scatter-gather support to the Marvell mv_or DMA driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Marcin Wojtas <mw@semihalf.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
202 lines
7.0 KiB
C
202 lines
7.0 KiB
C
/*
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* Copyright (C) 2007, 2008, Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef MV_XOR_H
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#define MV_XOR_H
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#define MV_XOR_POOL_SIZE (MV_XOR_SLOT_SIZE * 3072)
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#define MV_XOR_SLOT_SIZE 64
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#define MV_XOR_THRESHOLD 1
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#define MV_XOR_MAX_CHANNELS 2
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#define MV_XOR_MIN_BYTE_COUNT SZ_128
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#define MV_XOR_MAX_BYTE_COUNT (SZ_16M - 1)
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/* Values for the XOR_CONFIG register */
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#define XOR_OPERATION_MODE_XOR 0
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#define XOR_OPERATION_MODE_MEMCPY 2
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#define XOR_OPERATION_MODE_IN_DESC 7
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#define XOR_DESCRIPTOR_SWAP BIT(14)
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#define XOR_DESC_SUCCESS 0x40000000
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#define XOR_DESC_OPERATION_XOR (0 << 24)
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#define XOR_DESC_OPERATION_CRC32C (1 << 24)
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#define XOR_DESC_OPERATION_MEMCPY (2 << 24)
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#define XOR_DESC_DMA_OWNED BIT(31)
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#define XOR_DESC_EOD_INT_EN BIT(31)
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#define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4))
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#define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4))
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#define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4))
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#define XOR_DEST_POINTER(chan) (chan->mmr_high_base + 0xB0 + (chan->idx * 4))
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#define XOR_BLOCK_SIZE(chan) (chan->mmr_high_base + 0xC0 + (chan->idx * 4))
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#define XOR_INIT_VALUE_LOW(chan) (chan->mmr_high_base + 0xE0)
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#define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_high_base + 0xE4)
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#define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
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#define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
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#define XOR_INTR_CAUSE(chan) (chan->mmr_base + 0x30)
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#define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
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#define XOR_ERROR_CAUSE(chan) (chan->mmr_base + 0x50)
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#define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
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#define XOR_INT_END_OF_DESC BIT(0)
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#define XOR_INT_END_OF_CHAIN BIT(1)
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#define XOR_INT_STOPPED BIT(2)
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#define XOR_INT_PAUSED BIT(3)
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#define XOR_INT_ERR_DECODE BIT(4)
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#define XOR_INT_ERR_RDPROT BIT(5)
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#define XOR_INT_ERR_WRPROT BIT(6)
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#define XOR_INT_ERR_OWN BIT(7)
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#define XOR_INT_ERR_PAR BIT(8)
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#define XOR_INT_ERR_MBUS BIT(9)
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#define XOR_INTR_ERRORS (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \
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XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN | \
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XOR_INT_ERR_PAR | XOR_INT_ERR_MBUS)
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#define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | \
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XOR_INT_STOPPED | XOR_INTR_ERRORS)
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#define WINDOW_BASE(w) (0x50 + ((w) << 2))
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#define WINDOW_SIZE(w) (0x70 + ((w) << 2))
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#define WINDOW_REMAP_HIGH(w) (0x90 + ((w) << 2))
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#define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2))
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#define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2))
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#define WINDOW_COUNT 8
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struct mv_xor_device {
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void __iomem *xor_base;
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void __iomem *xor_high_base;
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struct clk *clk;
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struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS];
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int xor_type;
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u32 win_start[WINDOW_COUNT];
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u32 win_end[WINDOW_COUNT];
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};
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/**
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* struct mv_xor_chan - internal representation of a XOR channel
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* @pending: allows batching of hardware operations
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* @lock: serializes enqueue/dequeue operations to the descriptors pool
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* @mmr_base: memory mapped register base
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* @idx: the index of the xor channel
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* @chain: device chain view of the descriptors
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* @free_slots: free slots usable by the channel
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* @allocated_slots: slots allocated by the driver
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* @completed_slots: slots completed by HW but still need to be acked
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* @device: parent device
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* @common: common dmaengine channel object members
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* @slots_allocated: records the actual size of the descriptor slot pool
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* @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
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* @op_in_desc: new mode of driver, each op is writen to descriptor.
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*/
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struct mv_xor_chan {
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int pending;
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spinlock_t lock; /* protects the descriptor slot pool */
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void __iomem *mmr_base;
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void __iomem *mmr_high_base;
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unsigned int idx;
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int irq;
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struct list_head chain;
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struct list_head free_slots;
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struct list_head allocated_slots;
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struct list_head completed_slots;
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dma_addr_t dma_desc_pool;
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void *dma_desc_pool_virt;
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size_t pool_size;
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struct dma_device dmadev;
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struct dma_chan dmachan;
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int slots_allocated;
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struct tasklet_struct irq_tasklet;
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int op_in_desc;
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char dummy_src[MV_XOR_MIN_BYTE_COUNT];
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char dummy_dst[MV_XOR_MIN_BYTE_COUNT];
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dma_addr_t dummy_src_addr, dummy_dst_addr;
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u32 saved_config_reg, saved_int_mask_reg;
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struct mv_xor_device *xordev;
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};
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/**
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* struct mv_xor_desc_slot - software descriptor
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* @node: node on the mv_xor_chan lists
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* @hw_desc: virtual address of the hardware descriptor chain
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* @phys: hardware address of the hardware descriptor chain
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* @slot_used: slot in use or not
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* @idx: pool index
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* @tx_list: list of slots that make up a multi-descriptor transaction
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* @async_tx: support for the async_tx api
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*/
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struct mv_xor_desc_slot {
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struct list_head node;
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struct list_head sg_tx_list;
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enum dma_transaction_type type;
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void *hw_desc;
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u16 idx;
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struct dma_async_tx_descriptor async_tx;
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};
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/*
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* This structure describes XOR descriptor size 64bytes. The
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* mv_phy_src_idx() macro must be used when indexing the values of the
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* phy_src_addr[] array. This is due to the fact that the 'descriptor
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* swap' feature, used on big endian systems, swaps descriptors data
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* within blocks of 8 bytes. So two consecutive values of the
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* phy_src_addr[] array are actually swapped in big-endian, which
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* explains the different mv_phy_src_idx() implementation.
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*/
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#if defined(__LITTLE_ENDIAN)
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struct mv_xor_desc {
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u32 status; /* descriptor execution status */
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u32 crc32_result; /* result of CRC-32 calculation */
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u32 desc_command; /* type of operation to be carried out */
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u32 phy_next_desc; /* next descriptor address pointer */
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u32 byte_count; /* size of src/dst blocks in bytes */
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u32 phy_dest_addr; /* destination block address */
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u32 phy_src_addr[8]; /* source block addresses */
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u32 reserved0;
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u32 reserved1;
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};
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#define mv_phy_src_idx(src_idx) (src_idx)
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#else
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struct mv_xor_desc {
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u32 crc32_result; /* result of CRC-32 calculation */
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u32 status; /* descriptor execution status */
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u32 phy_next_desc; /* next descriptor address pointer */
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u32 desc_command; /* type of operation to be carried out */
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u32 phy_dest_addr; /* destination block address */
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u32 byte_count; /* size of src/dst blocks in bytes */
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u32 phy_src_addr[8]; /* source block addresses */
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u32 reserved1;
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u32 reserved0;
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};
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#define mv_phy_src_idx(src_idx) (src_idx ^ 1)
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#endif
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#define to_mv_sw_desc(addr_hw_desc) \
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container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
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#define mv_hw_desc_slot_idx(hw_desc, idx) \
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((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
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#endif
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