forked from luck/tmp_suning_uos_patched
783ab76ae5
With the A80 SoC, Allwinner grouped and moved some subsystem specific clock controls to a separate address space, and possibly separate hardware block. One such subsystem is the display engine. The main clock control unit now only has 1 set of bus gate, dram gate, module clock, and reset control for the entire display subsystem. These feed into a secondary clock control unit, which has controls for each individual module of the display pipeline. This block is not documented in the user manual. Allwinner's kernel was used as the reference. Add support for the display engine clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
||
|---|---|---|
| .. | ||
| arm | ||
| clk | ||
| clock | ||
| display | ||
| dma | ||
| gpio | ||
| i2c | ||
| iio | ||
| input | ||
| interrupt-controller | ||
| leds | ||
| mailbox | ||
| media | ||
| memory | ||
| mfd | ||
| net | ||
| phy | ||
| pinctrl | ||
| power | ||
| pwm | ||
| regulator | ||
| reset | ||
| soc | ||
| sound | ||
| spmi | ||
| thermal | ||