forked from luck/tmp_suning_uos_patched
a556c76adc
Add a driver for Microsemi Ocelot Ethernet switch support. This makes two modules: mscc_ocelot_common handles all the common features that doesn't depend on how the switch is integrated in the SoC. Currently, it handles offloading bridging to the hardware. ocelot_io.c handles register accesses. This is unfortunately needed because the register layout is packed and then depends on the number of ports available on the switch. The register definition files are automatically generated. ocelot_board handles the switch integration on the SoC and on the board. Frame injection and extraction to/from the CPU port is currently done using register accesses which is quite slow. DMA is possible but the port is not able to absorb the whole switch bandwidth. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
79 lines
3.8 KiB
C
79 lines
3.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Microsemi Ocelot Switch driver
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*
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#ifndef _MSCC_OCELOT_QS_H_
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#define _MSCC_OCELOT_QS_H_
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/* TODO handle BE */
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#define XTR_EOF_0 0x00000080U
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#define XTR_EOF_1 0x01000080U
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#define XTR_EOF_2 0x02000080U
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#define XTR_EOF_3 0x03000080U
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#define XTR_PRUNED 0x04000080U
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#define XTR_ABORT 0x05000080U
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#define XTR_ESCAPE 0x06000080U
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#define XTR_NOT_READY 0x07000080U
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#define XTR_VALID_BYTES(x) (4 - (((x) >> 24) & 3))
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#define QS_XTR_GRP_CFG_RSZ 0x4
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#define QS_XTR_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2))
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#define QS_XTR_GRP_CFG_MODE_M GENMASK(3, 2)
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#define QS_XTR_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
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#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
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#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
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#define QS_XTR_RD_RSZ 0x4
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#define QS_XTR_FRM_PRUNING_RSZ 0x4
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#define QS_XTR_CFG_DP_WM(x) (((x) << 5) & GENMASK(7, 5))
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#define QS_XTR_CFG_DP_WM_M GENMASK(7, 5)
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#define QS_XTR_CFG_DP_WM_X(x) (((x) & GENMASK(7, 5)) >> 5)
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#define QS_XTR_CFG_SCH_WM(x) (((x) << 2) & GENMASK(4, 2))
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#define QS_XTR_CFG_SCH_WM_M GENMASK(4, 2)
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#define QS_XTR_CFG_SCH_WM_X(x) (((x) & GENMASK(4, 2)) >> 2)
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#define QS_XTR_CFG_OFLW_ERR_STICKY(x) ((x) & GENMASK(1, 0))
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#define QS_XTR_CFG_OFLW_ERR_STICKY_M GENMASK(1, 0)
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#define QS_INJ_GRP_CFG_RSZ 0x4
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#define QS_INJ_GRP_CFG_MODE(x) (((x) << 2) & GENMASK(3, 2))
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#define QS_INJ_GRP_CFG_MODE_M GENMASK(3, 2)
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#define QS_INJ_GRP_CFG_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
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#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
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#define QS_INJ_WR_RSZ 0x4
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#define QS_INJ_CTRL_RSZ 0x4
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#define QS_INJ_CTRL_GAP_SIZE(x) (((x) << 21) & GENMASK(24, 21))
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#define QS_INJ_CTRL_GAP_SIZE_M GENMASK(24, 21)
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#define QS_INJ_CTRL_GAP_SIZE_X(x) (((x) & GENMASK(24, 21)) >> 21)
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#define QS_INJ_CTRL_ABORT BIT(20)
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#define QS_INJ_CTRL_EOF BIT(19)
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#define QS_INJ_CTRL_SOF BIT(18)
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#define QS_INJ_CTRL_VLD_BYTES(x) (((x) << 16) & GENMASK(17, 16))
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#define QS_INJ_CTRL_VLD_BYTES_M GENMASK(17, 16)
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#define QS_INJ_CTRL_VLD_BYTES_X(x) (((x) & GENMASK(17, 16)) >> 16)
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#define QS_INJ_STATUS_WMARK_REACHED(x) (((x) << 4) & GENMASK(5, 4))
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#define QS_INJ_STATUS_WMARK_REACHED_M GENMASK(5, 4)
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#define QS_INJ_STATUS_WMARK_REACHED_X(x) (((x) & GENMASK(5, 4)) >> 4)
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#define QS_INJ_STATUS_FIFO_RDY(x) (((x) << 2) & GENMASK(3, 2))
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#define QS_INJ_STATUS_FIFO_RDY_M GENMASK(3, 2)
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#define QS_INJ_STATUS_FIFO_RDY_X(x) (((x) & GENMASK(3, 2)) >> 2)
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#define QS_INJ_STATUS_INJ_IN_PROGRESS(x) ((x) & GENMASK(1, 0))
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#define QS_INJ_STATUS_INJ_IN_PROGRESS_M GENMASK(1, 0)
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#define QS_INJ_ERR_RSZ 0x4
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#define QS_INJ_ERR_ABORT_ERR_STICKY BIT(1)
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#define QS_INJ_ERR_WR_ERR_STICKY BIT(0)
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#endif
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