forked from luck/tmp_suning_uos_patched
c456cfc2e5
Based on 1 normalized pattern(s): released under the terms of the gnu gpl v2 0 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 9 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171439.076212120@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/sh/mm/tlb-sh4.c
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*
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* SH-4 specific TLB operations
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2002 - 2007 Paul Mundt
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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{
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unsigned long flags, pteval, vpn;
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/*
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* Handle debugger faulting in for debugee.
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*/
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if (vma && current->active_mm != vma->vm_mm)
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return;
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local_irq_save(flags);
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/* Set PTEH register */
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vpn = (address & MMU_VPN_MASK) | get_asid();
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__raw_writel(vpn, MMU_PTEH);
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pteval = pte.pte_low;
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/* Set PTEA register */
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#ifdef CONFIG_X2TLB
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/*
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* For the extended mode TLB this is trivial, only the ESZ and
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* EPR bits need to be written out to PTEA, with the remainder of
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* the protection bits (with the exception of the compat-mode SZ
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* and PR bits, which are cleared) being written out in PTEL.
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*/
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__raw_writel(pte.pte_high, MMU_PTEA);
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#else
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if (cpu_data->flags & CPU_HAS_PTEA) {
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/* The last 3 bits and the first one of pteval contains
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* the PTEA timing control and space attribute bits
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*/
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__raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
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}
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#endif
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/* Set PTEL register */
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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#ifdef CONFIG_CACHE_WRITETHROUGH
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pteval |= _PAGE_WT;
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#endif
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/* conveniently, we want all the software flags to be 0 anyway */
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__raw_writel(pteval, MMU_PTEL);
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/* Load the TLB */
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asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
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local_irq_restore(flags);
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}
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void local_flush_tlb_one(unsigned long asid, unsigned long page)
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{
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unsigned long addr, data;
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/*
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* NOTE: PTEH.ASID should be set to this MM
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* _AND_ we need to write ASID to the array.
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*
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* It would be simple if we didn't need to set PTEH.ASID...
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*/
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addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
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data = page | asid; /* VALID bit is off */
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jump_to_uncached();
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__raw_writel(data, addr);
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back_to_cached();
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}
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void local_flush_tlb_all(void)
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{
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unsigned long flags, status;
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int i;
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/*
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* Flush all the TLB.
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*/
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local_irq_save(flags);
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jump_to_uncached();
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status = __raw_readl(MMUCR);
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status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
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if (status == 0)
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status = MMUCR_URB_NENTRIES;
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for (i = 0; i < status; i++)
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__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
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for (i = 0; i < 4; i++)
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__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
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back_to_cached();
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ctrl_barrier();
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local_irq_restore(flags);
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}
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