forked from luck/tmp_suning_uos_patched
7d2284b09f
This patch restores the blackfin Hardware Performance Monitor Profiling
support that was killed by the combining of instrumentation menus in
commit 09cadedbdc.
Since there seems to be no good reason to behave differently from other
architectures, it now automatically selects the hardware performance
counters whenever the profiling is activated.
mach-common/irqpanic.c: pm_overflow calls pm_overflow_handler which is
in oprofile/op_model_bf533.c. I doubt that setting HARDWARE_PM as "m"
will work at all, since the pm_overflow_handler should be in the core
kernel image because it is called by irqpanic.c.
Therefore, I change HARDWARE_PM from a tristate to a bool.
The whole arch/$(ARCH)/oprofile/ is built depending on CONFIG_OPROFILE. Since
part of the HARDWARE_PM support files sits in this directory, it makes sense to
also depend on OPROFILE, not only PROFILING. Since OPROFILE already depends on
PROFILING, it is correct to only depend on OPROFILE only.
Thanks to Adrian Bunk for finding this bug and providing an initial
patch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
CC: Adrian Bunk <adrian.bunk@movial.fi>
CC: Randy Dunlap <randy.dunlap@oracle.com>
CC: bryan.wu@analog.com
Acked-by: Robin Getz <rgetz@blackfin.uclinux.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
1010 lines
22 KiB
Plaintext
1010 lines
22 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see Documentation/kbuild/kconfig-language.txt.
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#
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mainmenu "Blackfin Kernel Configuration"
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config MMU
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bool
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default n
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config FPU
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bool
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default n
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config RWSEM_GENERIC_SPINLOCK
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bool
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default y
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config RWSEM_XCHGADD_ALGORITHM
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bool
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default n
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config BLACKFIN
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bool
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default y
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config ZONE_DMA
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bool
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default y
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config SEMAPHORE_SLEEPERS
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bool
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default y
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config GENERIC_FIND_NEXT_BIT
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bool
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default y
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config GENERIC_HWEIGHT
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bool
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default y
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config GENERIC_HARDIRQS
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bool
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default y
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config GENERIC_IRQ_PROBE
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bool
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default y
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config GENERIC_TIME
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bool
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default n
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config GENERIC_GPIO
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bool
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default y
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config FORCE_MAX_ZONEORDER
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int
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default "14"
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config GENERIC_CALIBRATE_DELAY
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bool
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default y
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config HARDWARE_PM
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def_bool y
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depends on OPROFILE
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source "init/Kconfig"
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source "kernel/Kconfig.preempt"
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menu "Blackfin Processor Options"
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comment "Processor and Board Settings"
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choice
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prompt "CPU"
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default BF533
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config BF522
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bool "BF522"
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help
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BF522 Processor Support.
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config BF525
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bool "BF525"
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help
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BF525 Processor Support.
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config BF527
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bool "BF527"
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help
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BF527 Processor Support.
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config BF531
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bool "BF531"
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help
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BF531 Processor Support.
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config BF532
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bool "BF532"
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help
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BF532 Processor Support.
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config BF533
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bool "BF533"
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help
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BF533 Processor Support.
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config BF534
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bool "BF534"
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help
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BF534 Processor Support.
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config BF536
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bool "BF536"
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help
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BF536 Processor Support.
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config BF537
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bool "BF537"
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help
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BF537 Processor Support.
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config BF542
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bool "BF542"
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help
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BF542 Processor Support.
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config BF544
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bool "BF544"
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help
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BF544 Processor Support.
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config BF547
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bool "BF547"
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help
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BF547 Processor Support.
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config BF548
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bool "BF548"
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help
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BF548 Processor Support.
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config BF549
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bool "BF549"
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help
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BF549 Processor Support.
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config BF561
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bool "BF561"
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help
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Not Supported Yet - Work in progress - BF561 Processor Support.
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endchoice
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choice
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prompt "Silicon Rev"
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default BF_REV_0_1 if BF527
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default BF_REV_0_2 if BF537
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default BF_REV_0_3 if BF533
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default BF_REV_0_0 if BF549
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config BF_REV_0_0
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bool "0.0"
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depends on (BF52x || BF54x)
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config BF_REV_0_1
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bool "0.1"
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depends on (BF52x || BF54x)
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config BF_REV_0_2
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bool "0.2"
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depends on (BF537 || BF536 || BF534)
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config BF_REV_0_3
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bool "0.3"
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depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
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config BF_REV_0_4
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bool "0.4"
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depends on (BF561 || BF533 || BF532 || BF531)
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config BF_REV_0_5
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bool "0.5"
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depends on (BF561 || BF533 || BF532 || BF531)
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config BF_REV_ANY
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bool "any"
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config BF_REV_NONE
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bool "none"
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endchoice
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config BF52x
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bool
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depends on (BF522 || BF525 || BF527)
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default y
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config BF53x
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bool
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depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
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default y
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config BF54x
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bool
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depends on (BF542 || BF544 || BF547 || BF548 || BF549)
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default y
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config BFIN_DUAL_CORE
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bool
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depends on (BF561)
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default y
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config BFIN_SINGLE_CORE
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bool
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depends on !BFIN_DUAL_CORE
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default y
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config MEM_GENERIC_BOARD
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bool
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depends on GENERIC_BOARD
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default y
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config MEM_MT48LC64M4A2FB_7E
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bool
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depends on (BFIN533_STAMP)
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default y
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config MEM_MT48LC16M16A2TG_75
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bool
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depends on (BFIN533_EZKIT || BFIN561_EZKIT \
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|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
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|| H8606_HVSISTEMAS)
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default y
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config MEM_MT48LC32M8A2_75
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bool
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depends on (BFIN537_STAMP || PNAV10)
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default y
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config MEM_MT48LC8M32B2B5_7
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bool
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depends on (BFIN561_BLUETECHNIX_CM)
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default y
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config MEM_MT48LC32M16A2TG_75
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bool
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depends on (BFIN527_EZKIT)
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default y
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config BFIN_SHARED_FLASH_ENET
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bool
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depends on (BFIN533_STAMP)
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default y
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source "arch/blackfin/mach-bf527/Kconfig"
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source "arch/blackfin/mach-bf533/Kconfig"
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source "arch/blackfin/mach-bf561/Kconfig"
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source "arch/blackfin/mach-bf537/Kconfig"
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source "arch/blackfin/mach-bf548/Kconfig"
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menu "Board customizations"
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config CMDLINE_BOOL
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bool "Default bootloader kernel arguments"
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config CMDLINE
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string "Initial kernel command string"
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depends on CMDLINE_BOOL
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default "console=ttyBF0,57600"
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help
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If you don't have a boot loader capable of passing a command line string
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to the kernel, you may specify one here. As a minimum, you should specify
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the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
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comment "Clock/PLL Setup"
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config CLKIN_HZ
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int "Crystal Frequency in Hz"
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default "11059200" if BFIN533_STAMP
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default "27000000" if BFIN533_EZKIT
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default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
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default "30000000" if BFIN561_EZKIT
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default "24576000" if PNAV10
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help
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The frequency of CLKIN crystal oscillator on the board in Hz.
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config BFIN_KERNEL_CLOCK
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bool "Re-program Clocks while Kernel boots?"
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default n
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help
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This option decides if kernel clocks are re-programed from the
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bootloader settings. If the clocks are not set, the SDRAM settings
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are also not changed, and the Bootloader does 100% of the hardware
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configuration.
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config PLL_BYPASS
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bool "Bypass PLL"
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depends on BFIN_KERNEL_CLOCK
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default n
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config CLKIN_HALF
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bool "Half Clock In"
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depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
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default n
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help
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If this is set the clock will be divided by 2, before it goes to the PLL.
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config VCO_MULT
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int "VCO Multiplier"
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depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
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range 1 64
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default "22" if BFIN533_EZKIT
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default "45" if BFIN533_STAMP
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default "20" if (BFIN537_STAMP || BFIN527_EZKIT)
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default "22" if BFIN533_BLUETECHNIX_CM
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default "20" if BFIN537_BLUETECHNIX_CM
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default "20" if BFIN561_BLUETECHNIX_CM
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default "20" if BFIN561_EZKIT
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default "16" if H8606_HVSISTEMAS
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help
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This controls the frequency of the on-chip PLL. This can be between 1 and 64.
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PLL Frequency = (Crystal Frequency) * (this setting)
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choice
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prompt "Core Clock Divider"
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depends on BFIN_KERNEL_CLOCK
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default CCLK_DIV_1
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help
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This sets the frequency of the core. It can be 1, 2, 4 or 8
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Core Frequency = (PLL frequency) / (this setting)
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config CCLK_DIV_1
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bool "1"
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config CCLK_DIV_2
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bool "2"
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config CCLK_DIV_4
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bool "4"
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config CCLK_DIV_8
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bool "8"
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endchoice
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config SCLK_DIV
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int "System Clock Divider"
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depends on BFIN_KERNEL_CLOCK
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range 1 15
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default 5 if BFIN533_EZKIT
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default 5 if BFIN533_STAMP
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default 4 if (BFIN537_STAMP || BFIN527_EZKIT)
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default 5 if BFIN533_BLUETECHNIX_CM
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default 4 if BFIN537_BLUETECHNIX_CM
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default 4 if BFIN561_BLUETECHNIX_CM
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default 5 if BFIN561_EZKIT
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default 3 if H8606_HVSISTEMAS
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help
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This sets the frequency of the system clock (including SDRAM or DDR).
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This can be between 1 and 15
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System Clock = (PLL frequency) / (this setting)
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#
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# Max & Min Speeds for various Chips
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#
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config MAX_VCO_HZ
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int
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default 600000000 if BF522
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default 600000000 if BF525
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default 600000000 if BF527
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default 400000000 if BF531
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default 400000000 if BF532
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default 750000000 if BF533
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default 500000000 if BF534
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default 400000000 if BF536
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default 600000000 if BF537
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default 533333333 if BF538
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default 533333333 if BF539
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default 600000000 if BF542
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default 533333333 if BF544
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default 533333333 if BF549
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default 600000000 if BF561
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config MIN_VCO_HZ
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int
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default 50000000
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config MAX_SCLK_HZ
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int
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default 133333333
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config MIN_SCLK_HZ
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int
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default 27000000
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comment "Kernel Timer/Scheduler"
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source kernel/Kconfig.hz
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comment "Memory Setup"
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config MEM_SIZE
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int "SDRAM Memory Size in MBytes"
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default 32 if BFIN533_EZKIT
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default 64 if BFIN527_EZKIT
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default 64 if BFIN537_STAMP
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default 64 if BFIN561_EZKIT
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default 128 if BFIN533_STAMP
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default 64 if PNAV10
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default 32 if H8606_HVSISTEMAS
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config MEM_ADD_WIDTH
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int "SDRAM Memory Address Width"
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default 9 if BFIN533_EZKIT
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default 9 if BFIN561_EZKIT
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default 9 if H8606_HVSISTEMAS
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default 10 if BFIN527_EZKIT
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default 10 if BFIN537_STAMP
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default 11 if BFIN533_STAMP
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default 10 if PNAV10
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config ENET_FLASH_PIN
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int "PF port/pin used for flash and ethernet sharing"
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depends on (BFIN533_STAMP)
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default 0
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help
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PF port/pin used for flash and ethernet sharing to allow other PF
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pins to be used on other platforms without having to touch common
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code.
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For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
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config BOOT_LOAD
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hex "Kernel load address for booting"
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default "0x1000"
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range 0x1000 0x20000000
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help
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This option allows you to set the load address of the kernel.
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This can be useful if you are on a board which has a small amount
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of memory or you wish to reserve some memory at the beginning of
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the address space.
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Note that you need to keep this value above 4k (0x1000) as this
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memory region is used to capture NULL pointer references as well
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as some core kernel functions.
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comment "LED Status Indicators"
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depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
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config BFIN_ALIVE_LED
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bool "Enable Board Alive"
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depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
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default n
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help
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Blink the LEDs you select when the kernel is running. Helps detect
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a hung kernel.
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config BFIN_ALIVE_LED_NUM
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int "LED"
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depends on BFIN_ALIVE_LED
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range 1 3 if BFIN533_STAMP
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default "3" if BFIN533_STAMP
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help
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Select the LED (marked on the board) for you to blink.
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config BFIN_IDLE_LED
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bool "Enable System Load/Idle LED"
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depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
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default n
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help
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Blinks the LED you select when to determine kernel load.
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config BFIN_IDLE_LED_NUM
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int "LED"
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depends on BFIN_IDLE_LED
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range 1 3 if BFIN533_STAMP
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default "2" if BFIN533_STAMP
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help
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Select the LED (marked on the board) for you to blink.
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choice
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prompt "Blackfin Exception Scratch Register"
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default BFIN_SCRATCH_REG_RETN
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help
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Select the resource to reserve for the Exception handler:
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- RETN: Non-Maskable Interrupt (NMI)
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- RETE: Exception Return (JTAG/ICE)
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- CYCLES: Performance counter
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If you are unsure, please select "RETN".
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config BFIN_SCRATCH_REG_RETN
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bool "RETN"
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help
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Use the RETN register in the Blackfin exception handler
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as a stack scratch register. This means you cannot
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safely use NMI on the Blackfin while running Linux, but
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you can debug the system with a JTAG ICE and use the
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CYCLES performance registers.
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If you are unsure, please select "RETN".
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config BFIN_SCRATCH_REG_RETE
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bool "RETE"
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help
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Use the RETE register in the Blackfin exception handler
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as a stack scratch register. This means you cannot
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safely use a JTAG ICE while debugging a Blackfin board,
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but you can safely use the CYCLES performance registers
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and the NMI.
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If you are unsure, please select "RETN".
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config BFIN_SCRATCH_REG_CYCLES
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bool "CYCLES"
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help
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Use the CYCLES register in the Blackfin exception handler
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as a stack scratch register. This means you cannot
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safely use the CYCLES performance registers on a Blackfin
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board at anytime, but you can debug the system with a JTAG
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ICE and use the NMI.
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If you are unsure, please select "RETN".
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endchoice
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#
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# Sorry - but you need to put the hex address here -
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#
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# Flag Data register
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config BFIN_ALIVE_LED_PORT
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hex
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default 0xFFC00700 if (BFIN533_STAMP)
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# Peripheral Flag Direction Register
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config BFIN_ALIVE_LED_DPORT
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hex
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default 0xFFC00730 if (BFIN533_STAMP)
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config BFIN_ALIVE_LED_PIN
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hex
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default 0x04 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 1)
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default 0x08 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 2)
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default 0x10 if (BFIN533_STAMP && BFIN_ALIVE_LED_NUM = 3)
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config BFIN_IDLE_LED_PORT
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hex
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default 0xFFC00700 if (BFIN533_STAMP)
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# Peripheral Flag Direction Register
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config BFIN_IDLE_LED_DPORT
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hex
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default 0xFFC00730 if (BFIN533_STAMP)
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config BFIN_IDLE_LED_PIN
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hex
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default 0x04 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 1)
|
|
default 0x08 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 2)
|
|
default 0x10 if (BFIN533_STAMP && BFIN_IDLE_LED_NUM = 3)
|
|
|
|
endmenu
|
|
|
|
|
|
menu "Blackfin Kernel Optimizations"
|
|
|
|
comment "Memory Optimizations"
|
|
|
|
config I_ENTRY_L1
|
|
bool "Locate interrupt entry code in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config EXCPT_IRQ_SYSC_L1
|
|
bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, the entire ASM lowlevel exception and interrupt entry code
|
|
(STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
|
|
(less latency)
|
|
|
|
config DO_IRQ_L1
|
|
bool "Locate frequently called do_irq dispatcher function in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, the frequently called do_irq dispatcher function is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config CORE_TIMER_IRQ_L1
|
|
bool "Locate frequently called timer_interrupt() function in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, the frequently called timer_interrupt() function is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config IDLE_L1
|
|
bool "Locate frequently idle function in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, the frequently called idle function is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config SCHEDULE_L1
|
|
bool "Locate kernel schedule function in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, the frequently called kernel schedule is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config ARITHMETIC_OPS_L1
|
|
bool "Locate kernel owned arithmetic functions in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, arithmetic functions are linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config ACCESS_OK_L1
|
|
bool "Locate access_ok function in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, the access_ok function is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config MEMSET_L1
|
|
bool "Locate memset function in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, the memset function is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config MEMCPY_L1
|
|
bool "Locate memcpy function in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, the memcpy function is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config SYS_BFIN_SPINLOCK_L1
|
|
bool "Locate sys_bfin_spinlock function in L1 Memory"
|
|
default y
|
|
help
|
|
If enabled, sys_bfin_spinlock function is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config IP_CHECKSUM_L1
|
|
bool "Locate IP Checksum function in L1 Memory"
|
|
default n
|
|
help
|
|
If enabled, the IP Checksum function is linked
|
|
into L1 instruction memory. (less latency)
|
|
|
|
config CACHELINE_ALIGNED_L1
|
|
bool "Locate cacheline_aligned data to L1 Data Memory"
|
|
default y if !BF54x
|
|
default n if BF54x
|
|
depends on !BF531
|
|
help
|
|
If enabled, cacheline_anligned data is linked
|
|
into L1 data memory. (less latency)
|
|
|
|
config SYSCALL_TAB_L1
|
|
bool "Locate Syscall Table L1 Data Memory"
|
|
default n
|
|
depends on !BF531
|
|
help
|
|
If enabled, the Syscall LUT is linked
|
|
into L1 data memory. (less latency)
|
|
|
|
config CPLB_SWITCH_TAB_L1
|
|
bool "Locate CPLB Switch Tables L1 Data Memory"
|
|
default n
|
|
depends on !BF531
|
|
help
|
|
If enabled, the CPLB Switch Tables are linked
|
|
into L1 data memory. (less latency)
|
|
|
|
endmenu
|
|
|
|
|
|
choice
|
|
prompt "Kernel executes from"
|
|
help
|
|
Choose the memory type that the kernel will be running in.
|
|
|
|
config RAMKERNEL
|
|
bool "RAM"
|
|
help
|
|
The kernel will be resident in RAM when running.
|
|
|
|
config ROMKERNEL
|
|
bool "ROM"
|
|
help
|
|
The kernel will be resident in FLASH/ROM when running.
|
|
|
|
endchoice
|
|
|
|
source "mm/Kconfig"
|
|
|
|
config LARGE_ALLOCS
|
|
bool "Allow allocating large blocks (> 1MB) of memory"
|
|
help
|
|
Allow the slab memory allocator to keep chains for very large
|
|
memory sizes - upto 32MB. You may need this if your system has
|
|
a lot of RAM, and you need to able to allocate very large
|
|
contiguous chunks. If unsure, say N.
|
|
|
|
config BFIN_GPTIMERS
|
|
tristate "Enable Blackfin General Purpose Timers API"
|
|
default n
|
|
help
|
|
Enable support for the General Purpose Timers API. If you
|
|
are unsure, say N.
|
|
|
|
To compile this driver as a module, choose M here: the module
|
|
will be called gptimers.ko.
|
|
|
|
config BFIN_DMA_5XX
|
|
bool "Enable DMA Support"
|
|
depends on (BF52x || BF53x || BF561 || BF54x)
|
|
default y
|
|
help
|
|
DMA driver for BF5xx.
|
|
|
|
choice
|
|
prompt "Uncached SDRAM region"
|
|
default DMA_UNCACHED_1M
|
|
depends on BFIN_DMA_5XX
|
|
config DMA_UNCACHED_2M
|
|
bool "Enable 2M DMA region"
|
|
config DMA_UNCACHED_1M
|
|
bool "Enable 1M DMA region"
|
|
config DMA_UNCACHED_NONE
|
|
bool "Disable DMA region"
|
|
endchoice
|
|
|
|
|
|
comment "Cache Support"
|
|
config BFIN_ICACHE
|
|
bool "Enable ICACHE"
|
|
config BFIN_DCACHE
|
|
bool "Enable DCACHE"
|
|
config BFIN_DCACHE_BANKA
|
|
bool "Enable only 16k BankA DCACHE - BankB is SRAM"
|
|
depends on BFIN_DCACHE && !BF531
|
|
default n
|
|
config BFIN_ICACHE_LOCK
|
|
bool "Enable Instruction Cache Locking"
|
|
|
|
choice
|
|
prompt "Policy"
|
|
depends on BFIN_DCACHE
|
|
default BFIN_WB
|
|
config BFIN_WB
|
|
bool "Write back"
|
|
help
|
|
Write Back Policy:
|
|
Cached data will be written back to SDRAM only when needed.
|
|
This can give a nice increase in performance, but beware of
|
|
broken drivers that do not properly invalidate/flush their
|
|
cache.
|
|
|
|
Write Through Policy:
|
|
Cached data will always be written back to SDRAM when the
|
|
cache is updated. This is a completely safe setting, but
|
|
performance is worse than Write Back.
|
|
|
|
If you are unsure of the options and you want to be safe,
|
|
then go with Write Through.
|
|
|
|
config BFIN_WT
|
|
bool "Write through"
|
|
help
|
|
Write Back Policy:
|
|
Cached data will be written back to SDRAM only when needed.
|
|
This can give a nice increase in performance, but beware of
|
|
broken drivers that do not properly invalidate/flush their
|
|
cache.
|
|
|
|
Write Through Policy:
|
|
Cached data will always be written back to SDRAM when the
|
|
cache is updated. This is a completely safe setting, but
|
|
performance is worse than Write Back.
|
|
|
|
If you are unsure of the options and you want to be safe,
|
|
then go with Write Through.
|
|
|
|
endchoice
|
|
|
|
config L1_MAX_PIECE
|
|
int "Set the max L1 SRAM pieces"
|
|
default 16
|
|
help
|
|
Set the max memory pieces for the L1 SRAM allocation algorithm.
|
|
Min value is 16. Max value is 1024.
|
|
|
|
comment "Asynchonous Memory Configuration"
|
|
|
|
menu "EBIU_AMGCTL Global Control"
|
|
config C_AMCKEN
|
|
bool "Enable CLKOUT"
|
|
default y
|
|
|
|
config C_CDPRIO
|
|
bool "DMA has priority over core for ext. accesses"
|
|
depends on !BF54x
|
|
default n
|
|
|
|
config C_B0PEN
|
|
depends on BF561
|
|
bool "Bank 0 16 bit packing enable"
|
|
default y
|
|
|
|
config C_B1PEN
|
|
depends on BF561
|
|
bool "Bank 1 16 bit packing enable"
|
|
default y
|
|
|
|
config C_B2PEN
|
|
depends on BF561
|
|
bool "Bank 2 16 bit packing enable"
|
|
default y
|
|
|
|
config C_B3PEN
|
|
depends on BF561
|
|
bool "Bank 3 16 bit packing enable"
|
|
default n
|
|
|
|
choice
|
|
prompt"Enable Asynchonous Memory Banks"
|
|
default C_AMBEN_ALL
|
|
|
|
config C_AMBEN
|
|
bool "Disable All Banks"
|
|
|
|
config C_AMBEN_B0
|
|
bool "Enable Bank 0"
|
|
|
|
config C_AMBEN_B0_B1
|
|
bool "Enable Bank 0 & 1"
|
|
|
|
config C_AMBEN_B0_B1_B2
|
|
bool "Enable Bank 0 & 1 & 2"
|
|
|
|
config C_AMBEN_ALL
|
|
bool "Enable All Banks"
|
|
endchoice
|
|
endmenu
|
|
|
|
menu "EBIU_AMBCTL Control"
|
|
config BANK_0
|
|
hex "Bank 0"
|
|
default 0x7BB0
|
|
|
|
config BANK_1
|
|
hex "Bank 1"
|
|
default 0x7BB0
|
|
|
|
config BANK_2
|
|
hex "Bank 2"
|
|
default 0x7BB0
|
|
|
|
config BANK_3
|
|
hex "Bank 3"
|
|
default 0x99B3
|
|
endmenu
|
|
|
|
config EBIU_MBSCTLVAL
|
|
hex "EBIU Bank Select Control Register"
|
|
depends on BF54x
|
|
default 0
|
|
|
|
config EBIU_MODEVAL
|
|
hex "Flash Memory Mode Control Register"
|
|
depends on BF54x
|
|
default 1
|
|
|
|
config EBIU_FCTLVAL
|
|
hex "Flash Memory Bank Control Register"
|
|
depends on BF54x
|
|
default 6
|
|
endmenu
|
|
|
|
#############################################################################
|
|
menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
|
|
|
|
config PCI
|
|
bool "PCI support"
|
|
help
|
|
Support for PCI bus.
|
|
|
|
source "drivers/pci/Kconfig"
|
|
|
|
config HOTPLUG
|
|
bool "Support for hot-pluggable device"
|
|
help
|
|
Say Y here if you want to plug devices into your computer while
|
|
the system is running, and be able to use them quickly. In many
|
|
cases, the devices can likewise be unplugged at any time too.
|
|
|
|
One well known example of this is PCMCIA- or PC-cards, credit-card
|
|
size devices such as network cards, modems or hard drives which are
|
|
plugged into slots found on all modern laptop computers. Another
|
|
example, used on modern desktops as well as laptops, is USB.
|
|
|
|
Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
|
|
software (at <http://linux-hotplug.sourceforge.net/>) and install it.
|
|
Then your kernel will automatically call out to a user mode "policy
|
|
agent" (/sbin/hotplug) to load modules and set up software needed
|
|
to use devices as you hotplug them.
|
|
|
|
source "drivers/pcmcia/Kconfig"
|
|
|
|
source "drivers/pci/hotplug/Kconfig"
|
|
|
|
endmenu
|
|
|
|
menu "Executable file formats"
|
|
|
|
source "fs/Kconfig.binfmt"
|
|
|
|
endmenu
|
|
|
|
menu "Power management options"
|
|
source "kernel/power/Kconfig"
|
|
|
|
choice
|
|
prompt "Select PM Wakeup Event Source"
|
|
default PM_WAKEUP_GPIO_BY_SIC_IWR
|
|
depends on PM
|
|
help
|
|
If you have a GPIO already configured as input with the corresponding PORTx_MASK
|
|
bit set - "Specify Wakeup Event by SIC_IWR value"
|
|
|
|
config PM_WAKEUP_GPIO_BY_SIC_IWR
|
|
bool "Specify Wakeup Event by SIC_IWR value"
|
|
config PM_WAKEUP_BY_GPIO
|
|
bool "Cause Wakeup Event by GPIO"
|
|
config PM_WAKEUP_GPIO_API
|
|
bool "Configure Wakeup Event by PM GPIO API"
|
|
|
|
endchoice
|
|
|
|
config PM_WAKEUP_SIC_IWR
|
|
hex "Wakeup Events (SIC_IWR)"
|
|
depends on PM_WAKEUP_GPIO_BY_SIC_IWR
|
|
default 0x80000000 if (BF537 || BF536 || BF534)
|
|
default 0x100000 if (BF533 || BF532 || BF531)
|
|
|
|
config PM_WAKEUP_GPIO_NUMBER
|
|
int "Wakeup GPIO number"
|
|
range 0 47
|
|
depends on PM_WAKEUP_BY_GPIO
|
|
default 2 if BFIN537_STAMP
|
|
|
|
choice
|
|
prompt "GPIO Polarity"
|
|
depends on PM_WAKEUP_BY_GPIO
|
|
default PM_WAKEUP_GPIO_POLAR_H
|
|
config PM_WAKEUP_GPIO_POLAR_H
|
|
bool "Active High"
|
|
config PM_WAKEUP_GPIO_POLAR_L
|
|
bool "Active Low"
|
|
config PM_WAKEUP_GPIO_POLAR_EDGE_F
|
|
bool "Falling EDGE"
|
|
config PM_WAKEUP_GPIO_POLAR_EDGE_R
|
|
bool "Rising EDGE"
|
|
config PM_WAKEUP_GPIO_POLAR_EDGE_B
|
|
bool "Both EDGE"
|
|
endchoice
|
|
|
|
endmenu
|
|
|
|
if (BF537 || BF533 || BF54x)
|
|
|
|
menu "CPU Frequency scaling"
|
|
|
|
source "drivers/cpufreq/Kconfig"
|
|
|
|
config CPU_FREQ
|
|
bool
|
|
default n
|
|
help
|
|
If you want to enable this option, you should select the
|
|
DPMC driver from Character Devices.
|
|
endmenu
|
|
|
|
endif
|
|
|
|
source "net/Kconfig"
|
|
|
|
source "drivers/Kconfig"
|
|
|
|
source "fs/Kconfig"
|
|
|
|
source "kernel/Kconfig.instrumentation"
|
|
|
|
source "arch/blackfin/Kconfig.debug"
|
|
|
|
source "security/Kconfig"
|
|
|
|
source "crypto/Kconfig"
|
|
|
|
source "lib/Kconfig"
|