forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
456 lines
11 KiB
C
456 lines
11 KiB
C
/*
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* giu.c, General-purpose I/O Unit Interrupt routines for NEC VR4100 series.
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*
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* Copyright (C) 2002 MontaVista Software Inc.
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* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
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* Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Changes:
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* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
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* - New creation, NEC VR4111, VR4121, VR4122 and VR4131 are supported.
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*
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* Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
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* - Added support for NEC VR4133.
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* - Removed board_irq_init.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/vr41xx/vr41xx.h>
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#define GIUIOSELL_TYPE1 KSEG1ADDR(0x0b000100)
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#define GIUIOSELL_TYPE2 KSEG1ADDR(0x0f000140)
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#define GIUIOSELL 0x00
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#define GIUIOSELH 0x02
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#define GIUINTSTATL 0x08
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#define GIUINTSTATH 0x0a
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#define GIUINTENL 0x0c
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#define GIUINTENH 0x0e
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#define GIUINTTYPL 0x10
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#define GIUINTTYPH 0x12
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#define GIUINTALSELL 0x14
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#define GIUINTALSELH 0x16
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#define GIUINTHTSELL 0x18
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#define GIUINTHTSELH 0x1a
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#define GIUFEDGEINHL 0x20
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#define GIUFEDGEINHH 0x22
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#define GIUREDGEINHL 0x24
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#define GIUREDGEINHH 0x26
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static uint32_t giu_base;
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static struct irqaction giu_cascade = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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#define read_giuint(offset) readw(giu_base + (offset))
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#define write_giuint(val, offset) writew((val), giu_base + (offset))
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#define GIUINT_HIGH_OFFSET 16
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static inline uint16_t set_giuint(uint8_t offset, uint16_t set)
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{
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uint16_t res;
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res = read_giuint(offset);
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res |= set;
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write_giuint(res, offset);
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return res;
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}
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static inline uint16_t clear_giuint(uint8_t offset, uint16_t clear)
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{
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uint16_t res;
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res = read_giuint(offset);
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res &= ~clear;
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write_giuint(res, offset);
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return res;
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}
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static unsigned int startup_giuint_low_irq(unsigned int irq)
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{
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unsigned int pin;
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pin = GIU_IRQ_TO_PIN(irq);
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write_giuint((uint16_t)1 << pin, GIUINTSTATL);
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set_giuint(GIUINTENL, (uint16_t)1 << pin);
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return 0;
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}
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static void shutdown_giuint_low_irq(unsigned int irq)
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{
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clear_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
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}
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static void enable_giuint_low_irq(unsigned int irq)
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{
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set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
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}
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#define disable_giuint_low_irq shutdown_giuint_low_irq
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static void ack_giuint_low_irq(unsigned int irq)
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{
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unsigned int pin;
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pin = GIU_IRQ_TO_PIN(irq);
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clear_giuint(GIUINTENL, (uint16_t)1 << pin);
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write_giuint((uint16_t)1 << pin, GIUINTSTATL);
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}
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static void end_giuint_low_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
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}
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static struct hw_interrupt_type giuint_low_irq_type = {
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.typename = "GIUINTL",
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.startup = startup_giuint_low_irq,
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.shutdown = shutdown_giuint_low_irq,
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.enable = enable_giuint_low_irq,
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.disable = disable_giuint_low_irq,
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.ack = ack_giuint_low_irq,
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.end = end_giuint_low_irq,
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};
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static unsigned int startup_giuint_high_irq(unsigned int irq)
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{
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unsigned int pin;
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pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET);
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write_giuint((uint16_t)1 << pin, GIUINTSTATH);
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set_giuint(GIUINTENH, (uint16_t)1 << pin);
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return 0;
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}
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static void shutdown_giuint_high_irq(unsigned int irq)
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{
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clear_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
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}
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static void enable_giuint_high_irq(unsigned int irq)
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{
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set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
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}
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#define disable_giuint_high_irq shutdown_giuint_high_irq
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static void ack_giuint_high_irq(unsigned int irq)
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{
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unsigned int pin;
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pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET);
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clear_giuint(GIUINTENH, (uint16_t)1 << pin);
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write_giuint((uint16_t)1 << pin, GIUINTSTATH);
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}
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static void end_giuint_high_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
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}
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static struct hw_interrupt_type giuint_high_irq_type = {
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.typename = "GIUINTH",
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.startup = startup_giuint_high_irq,
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.shutdown = shutdown_giuint_high_irq,
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.enable = enable_giuint_high_irq,
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.disable = disable_giuint_high_irq,
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.ack = ack_giuint_high_irq,
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.end = end_giuint_high_irq,
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};
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void __init init_vr41xx_giuint_irq(void)
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{
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int i;
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for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
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if (i < (GIU_IRQ_BASE + GIUINT_HIGH_OFFSET))
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irq_desc[i].handler = &giuint_low_irq_type;
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else
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irq_desc[i].handler = &giuint_high_irq_type;
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}
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setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade);
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}
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void vr41xx_set_irq_trigger(int pin, int trigger, int hold)
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{
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uint16_t mask;
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if (pin < GIUINT_HIGH_OFFSET) {
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mask = (uint16_t)1 << pin;
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if (trigger != TRIGGER_LEVEL) {
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set_giuint(GIUINTTYPL, mask);
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if (hold == SIGNAL_HOLD)
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set_giuint(GIUINTHTSELL, mask);
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else
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clear_giuint(GIUINTHTSELL, mask);
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if (current_cpu_data.cputype == CPU_VR4133) {
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switch (trigger) {
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case TRIGGER_EDGE_FALLING:
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set_giuint(GIUFEDGEINHL, mask);
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clear_giuint(GIUREDGEINHL, mask);
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break;
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case TRIGGER_EDGE_RISING:
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clear_giuint(GIUFEDGEINHL, mask);
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set_giuint(GIUREDGEINHL, mask);
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break;
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default:
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set_giuint(GIUFEDGEINHL, mask);
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set_giuint(GIUREDGEINHL, mask);
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break;
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}
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}
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} else {
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clear_giuint(GIUINTTYPL, mask);
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clear_giuint(GIUINTHTSELL, mask);
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}
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write_giuint(mask, GIUINTSTATL);
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} else {
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mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET);
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if (trigger != TRIGGER_LEVEL) {
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set_giuint(GIUINTTYPH, mask);
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if (hold == SIGNAL_HOLD)
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set_giuint(GIUINTHTSELH, mask);
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else
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clear_giuint(GIUINTHTSELH, mask);
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if (current_cpu_data.cputype == CPU_VR4133) {
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switch (trigger) {
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case TRIGGER_EDGE_FALLING:
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set_giuint(GIUFEDGEINHH, mask);
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clear_giuint(GIUREDGEINHH, mask);
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break;
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case TRIGGER_EDGE_RISING:
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clear_giuint(GIUFEDGEINHH, mask);
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set_giuint(GIUREDGEINHH, mask);
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break;
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default:
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set_giuint(GIUFEDGEINHH, mask);
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set_giuint(GIUREDGEINHH, mask);
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break;
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}
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}
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} else {
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clear_giuint(GIUINTTYPH, mask);
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clear_giuint(GIUINTHTSELH, mask);
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}
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write_giuint(mask, GIUINTSTATH);
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}
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}
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EXPORT_SYMBOL(vr41xx_set_irq_trigger);
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void vr41xx_set_irq_level(int pin, int level)
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{
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uint16_t mask;
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if (pin < GIUINT_HIGH_OFFSET) {
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mask = (uint16_t)1 << pin;
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if (level == LEVEL_HIGH)
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set_giuint(GIUINTALSELL, mask);
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else
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clear_giuint(GIUINTALSELL, mask);
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write_giuint(mask, GIUINTSTATL);
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} else {
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mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET);
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if (level == LEVEL_HIGH)
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set_giuint(GIUINTALSELH, mask);
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else
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clear_giuint(GIUINTALSELH, mask);
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write_giuint(mask, GIUINTSTATH);
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}
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}
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EXPORT_SYMBOL(vr41xx_set_irq_level);
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#define GIUINT_NR_IRQS 32
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enum {
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GIUINT_NO_CASCADE,
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GIUINT_CASCADE
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};
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struct vr41xx_giuint_cascade {
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unsigned int flag;
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int (*get_irq_number)(int irq);
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};
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static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS];
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static int no_irq_number(int irq)
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{
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return -EINVAL;
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}
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int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq))
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{
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unsigned int pin;
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int retval;
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if (irq < GIU_IRQ(0) || irq > GIU_IRQ(31))
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return -EINVAL;
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if(!get_irq_number)
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return -EINVAL;
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pin = GIU_IRQ_TO_PIN(irq);
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giuint_cascade[pin].flag = GIUINT_CASCADE;
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giuint_cascade[pin].get_irq_number = get_irq_number;
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retval = setup_irq(irq, &giu_cascade);
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if (retval != 0) {
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giuint_cascade[pin].flag = GIUINT_NO_CASCADE;
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giuint_cascade[pin].get_irq_number = no_irq_number;
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}
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return retval;
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}
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EXPORT_SYMBOL(vr41xx_cascade_irq);
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static inline int get_irq_pin_number(void)
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{
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uint16_t pendl, pendh, maskl, maskh;
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int i;
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pendl = read_giuint(GIUINTSTATL);
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pendh = read_giuint(GIUINTSTATH);
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maskl = read_giuint(GIUINTENL);
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maskh = read_giuint(GIUINTENH);
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maskl &= pendl;
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maskh &= pendh;
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if (maskl) {
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for (i = 0; i < 16; i++) {
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if (maskl & ((uint16_t)1 << i))
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return i;
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}
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} else if (maskh) {
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for (i = 0; i < 16; i++) {
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if (maskh & ((uint16_t)1 << i))
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return i + GIUINT_HIGH_OFFSET;
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}
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}
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printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
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maskl, pendl, maskh, pendh);
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atomic_inc(&irq_err_count);
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return -1;
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}
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static inline void ack_giuint_irq(int pin)
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{
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if (pin < GIUINT_HIGH_OFFSET) {
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clear_giuint(GIUINTENL, (uint16_t)1 << pin);
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write_giuint((uint16_t)1 << pin, GIUINTSTATL);
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} else {
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pin -= GIUINT_HIGH_OFFSET;
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clear_giuint(GIUINTENH, (uint16_t)1 << pin);
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write_giuint((uint16_t)1 << pin, GIUINTSTATH);
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}
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}
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static inline void end_giuint_irq(int pin)
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{
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if (pin < GIUINT_HIGH_OFFSET)
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set_giuint(GIUINTENL, (uint16_t)1 << pin);
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else
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set_giuint(GIUINTENH, (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET));
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}
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void giuint_irq_dispatch(struct pt_regs *regs)
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{
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struct vr41xx_giuint_cascade *cascade;
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unsigned int giuint_irq;
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int pin;
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pin = get_irq_pin_number();
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if (pin < 0)
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return;
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disable_irq(GIUINT_CASCADE_IRQ);
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cascade = &giuint_cascade[pin];
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giuint_irq = GIU_IRQ(pin);
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if (cascade->flag == GIUINT_CASCADE) {
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int irq = cascade->get_irq_number(giuint_irq);
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ack_giuint_irq(pin);
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if (irq >= 0)
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do_IRQ(irq, regs);
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end_giuint_irq(pin);
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} else {
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do_IRQ(giuint_irq, regs);
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}
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enable_irq(GIUINT_CASCADE_IRQ);
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}
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static int __init vr41xx_giu_init(void)
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{
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int i;
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switch (current_cpu_data.cputype) {
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case CPU_VR4111:
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case CPU_VR4121:
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giu_base = GIUIOSELL_TYPE1;
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break;
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case CPU_VR4122:
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case CPU_VR4131:
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case CPU_VR4133:
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giu_base = GIUIOSELL_TYPE2;
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break;
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default:
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printk(KERN_ERR "GIU: Unexpected CPU of NEC VR4100 series\n");
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return -EINVAL;
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}
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for (i = 0; i < GIUINT_NR_IRQS; i++) {
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if (i < GIUINT_HIGH_OFFSET)
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clear_giuint(GIUINTENL, (uint16_t)1 << i);
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else
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clear_giuint(GIUINTENH, (uint16_t)1 << (i - GIUINT_HIGH_OFFSET));
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giuint_cascade[i].flag = GIUINT_NO_CASCADE;
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giuint_cascade[i].get_irq_number = no_irq_number;
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}
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return 0;
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}
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early_initcall(vr41xx_giu_init);
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